Inter national J our nal of Recongurable and Embedded Systems (IJRES) V ol. 15, No. 2, July 2026, pp. 373 ∼ 385 ISSN: 2089-4864, DOI: 10.11591/ijres.v15.i2.pp373-385 ❒ 373 Cr o w sear ch algorithm f or efcient IP placement in 2D and 3D netw ork-on-chip ar chitectur es Maamar Bougherara 1,2 , Amina Guidoum 1 , Rak Amara 1,3 1 Department of Computer Science, High Normal School of K ouba, Algiers, Algeria 2 LIM Laboratory , F aculty of Exact Sciences, Akli Mohand Oulhadj Uni v ersity of Bouira, Bouira, Algeria 3 L TIR Laboratory , F aculty of Electronics and Computational Science, USTHB Uni v ersity , Algiers, Algeria Article Inf o Article history: Recei v ed Dec 26, 2025 Re vised Apr 12, 2026 Accepted May 31, 2026 K eyw ords: Communication cost Cro w search algorithm Netw ork-on-chip Optimization Placement ABSTRA CT The communication in system-on-chip (SoC) has e v olv ed to meet the increas- ingly comple x requirements of modern applications. T o addr ess connecti vity challenges, the netw ork-on-chip (NoC) has emer ged as an ef c ient solution. While traditional NoCs are primarily based on 2D architectures, the inherent limitations of 2D designs ha v e dri v en the adoption of 3D architectures, which of fer enhanced space utilization and performance optimization. A k e y step in the design of NoC systems is the placement of cores, also kno wn as the map- ping phase, in which application tasks are assigned to the archite cture’ s process- ing elements. This phase is considered an nondeterministic polynomial (NP)- complete problem due to its combinatorial comple xity . Optimizing this phase is crucial, as it directly impacts the o v erall performance of the NoC. V arious opti- mization algorithms ha v e been emplo yed to maximize the ef cienc y of 2D and 3D NoCs. In this paper , we adopt the cro w search algorithm to nd the places both 2D and 3D NoCs with minimal comunication. The goal is to e v aluate its performance compared to other optimization algorithms in this crucial step. This is an open access article under the CC BY -SA license . Corresponding A uthor: Maamar Bougherara Department of Computer Science, High Normal School of K ouba Algiers, Algeria Email: bougherara.maamar@gmail.com 1. INTR ODUCTION The increasing comple xity of modern system-on-chip (SoC) designs, characterized by the int e g r ation of numerous processing elements on a single chip, has made ef cient on-chip communication a critical chal- lenge. T raditional b us-based inter connection architectures suf fer from scalability limitations, bandwidth con- straints, and increased po wer consumption, making them unsuitable for lar ge-scale systems. T o o v ercome these limitations, netw ork-on-chip (NoC) architectures h a v e emer ged as an ef cient communication paradigm. In- spired by con v entional computer netw orks, NoC pro vides a scalable and structured communication frame w ork based on routers and pack et-switched data transfer , enabling ef cient communication among multiple on-chip components. In v ery lar ge scale inte gration (VLSI) systems, NoC helps manage communication comple xity , impro v es modularity , and reduces interconnection delays. Moreo v er , in embedded systems, NoC f acilitates ef cient data e xchange between processing units whil e maintaining high performance and ener gy ef cienc y . Consequently , NoC has become a k e y technology for addressing communication bottlenecks and enabling the design of scalable and high-performance computing systems [1]. In NoC-based systems, applications are typically di vided into se v eral computational tasks, each en- J ournal homepage: http://ijr es.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
374 ❒ ISSN: 2089-4864 capsulated in an intellectual property (IP) block. Thes e IPs must be inte grated into the NoC infrastructure in a manner that maximizes performance while minimizing ener gy consumption and latenc y [2]. A typical NoC consists of four k e y components [3] IP cores, which include processors, memory units, and custom controllers, netw ork interf aces (NIs), which serv e as a bridge between the IP cores and the NoC communication f abric; routers, which handle pack et forw arding and arbitration; and ph ysical interconnects, which dene the paths for data transmission. The topology of a NoC determines ho w tiles are connected [4]. Among the dif ferent topol- ogy options, the 2D mesh remains the most pre v alent choice, lar gely attrib uted to its highl y re gular and scalable structure. W ith the increasing comple xity and inte gration density of modern SoCs, 2D NoC architectures f ace gro wing limitations in terms of bandwidth, latenc y , and ener gy ef cienc y . T o address these challenges, three- dimensional (3D) NoC archi tectures ha v e been proposed [2]. By v ertically stacking multiple 2D layers and emplo ying through-silicon V ia (TSV) technology [2], 3D NoCs si g ni cantly reduce the a v erage communica- tion distance, enhance bandwidth, and impro v e performance. In a 3D mesh topology , each router connects to up to six neighboring routers [4]: four in the same layer and tw o in adjacent v ertical layers. This congura- tion enables both intra-layer and inter -layer communication, leading to better parallelism, reduced latenc y , and higher throughput. Figure 1 illustrates e xamples of NoC architectures topologies. The 2D mesh consists of 9 tiles arranged in a ( 3 × 3 ) grid (Figure 1(a)), whereas the 3D mesh architecture consists of 27 cores or g anized in a ( 3 × 3 × 3 ) structure (Figure 1(b)). (a) (b) Figure 1. Mesh-based NoC: (a) 2D and (b) 3D The design of a NoC-based system generally follo ws three main stages [3]: task assignment, which in v olv es assigning application tasks to a predened library of IP blocks, IP pl acement, where these IP blocks are mapped to ph ysical nodes (routers) within the NoC and static routing, which determines the communication paths between the mapped IPs. Each of these stages is supported by electronic design automation (ED A) tools, which e xplore the design space search to generate optimized hardw are/softw are congurations. Figure 2 illustrates a standard embedded system design o w for NoC platforms. IP core placement in NoC architectures signicantly af fects system performance. Poor placement increases communication latenc y and po wer consumption due to longer distances between communicating cores. It may also cause netw ork congestion and limits scal ability in lar ge man y-core systems. Therefore, ef cient placement strate gies are essential to optimize communication cost and impro v e o v erall system performance. This paper introduces a no v el model for solving the IP placement problem in both 2D and 3D NoCs. After modeling the problem, dening the main objecti v e of the study , and formulating the cost function, the cro w search algorithm (CSA) is emplo yed for the rst time as a ne w method to address the application placement problem. The structure of this paper is as follo ws: section 2 presentes the NoC topology and formulates the placement problem. Section 3 pro vides a re vie w of prior research related to placement in NoC architectures. In section 4, we present the modeling of the placement problem prior to applying a metaheuristic approach. The CSA, used as the core placement strate gy , is described in section 5. Section 6 analyzes the results obtained from the simulation e xperiments. Finally , section 7 presents the conclusion of the study along with directions for future w ork. Int J Recongurable & Embedded Syst, V ol. 15, No. 2, July 2026: 373–385 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 375 Figure 2. T ypical embedded system design o w for NoC platform 2. NETW ORK T OPOLOGY AND PLA CEMENT PR OBLEM In con v entional 2D NoCs, each IP is connected t o a rout er via a NI, and these rout ers are arranged in a planar grid with wired links. Communication tak es place using pack et-swi tched data transfer , where messages are brok en into pack ets and routed through the NoC [5]. Compared to traditional b us-based systems, 2D NoCs of fer se v eral adv antages: higher communication bandwidth, reduced latenc y , impro v ed scalability , and lo wer po wer consumption [6]. Ho we v er , as more IPs are inte grated into a single chip, the a v erage number of hops (routers tra v ersed by a pack et) increases, leading to greater communication ener gy and de graded performance. This issue becomes increasingly problematic as system size gro ws [4]. The 3D NoC paradigm addresses these issues by enabling v ertical communication through TSVs. This approach reduces the a v erage hop count and signicantly lo wers latenc y and ener gy consumption. Additionally , it enhances area utilization, making it suitable for lar ge-scale multicore systems. Consequently , 3D NoCs ha v e g ained signicant interest in both academia and industry as a compel ling solution for future high-performance computing platforms. This w ork focuses on optimizing the placement phases of NoC design, aiming to minimize communication ener gy while maintaining high system performance. In a 3D NoC, the IP placement problem consists of assigning each IP core to a specic node within the 3D topology . This phase is critical, as ef cient placement can greatly reduce communication cost, ener gy usage, and latenc y [4]. Due to its com binatorial nature, the IP placement problem is considered nondeterministic polynomial (NP)-hard and is closely related to the quadratic assignment problem (QAP). This comple xity mak es e xact solutions impractical for lar ge systems, especially within limited design time. As 3D NoCs enable the inte gration of a greater number of IPs across multiple layers using TSVs, ef cient and scalable placement algorithms are becoming increasingly important. T o tackle this problem, heuristic and met aheuristic techniques represent a practical soluti on , as the y can ef ciently generate high-quality approximat ions within a reasonable computation time. F or e xample, when assigning m tasks to a NoC with n cores where ( m < = n ) , the number of possible placement congurations may gro w as lar ge as n ! / ( n − m )! . 3. RELA TED W ORK Se v eral approaches ha v e been proposed to address the placement problem in NoC architectures, com- monly referred to as the mapping problem. These mapping techniques can be classied into three principal cate gories: e xact approaches, heuristic (or approximate) techniques, and metaheuristic methods [7]. This paper presents an o v ervie w of the most highly cited w orks that address the problem using a single-objecti v e approach. In e xact mapping methods, such as e xhausti v e search, linear programming, and branch-and-bound algorithms, rely on mathematical rigor to guarantee globally optimal solutions. An inte ger linear programming (ILP) formulation for the IP mapping problem is pr esented in [8]. This approach models both objecti v es and constraints as linear functions, with the additional requirement that decision v ariables tak e inte ger v alues. The ILP model is solv ed using the FICO Xpress optimization tool, enabling precise solution computation within a mathematically dened space. Despite their accurac y , e xact methods suf fer from high computational comple x- Cr ow sear c h algorithm for ef cient IP placement in 2D and 3D network-on-c hip ... (Maamar Bougher ar a) Evaluation Warning : The document was created with Spire.PDF for Python.
376 ❒ ISSN: 2089-4864 ity and signicant runtime requirements. As a result, the y are typically feasible only for small-scale mapping scenarios in v olving a limited number of IP cores, where the size of the solution space remains manageable under current computing capabilities. The second cate gory encompasses heuristic-based approaches , which aim to pro vide ef cient and practical solutions to the application mapping problem on NoC architectures. The NMAP algorithm [9] is a widely used heuristic that maps application cores to tiles i terati v ely . At each step, a core is selected and assigned to a tile, repeating the process until all cores are mapped. While NMAP includes an iterati v e impro v e- ment mechanism, the quality of the nal solutions often remains constrained by the initial mapping. BMAP [10] introduces a binomial mapping approach based on iterati v e tw o-w ay mer ging, taking into account the traf c load between cores to optimize communication. CastNet [11] enhances solution di v ersity by le v eraging the symmetric characteristics of mesh topologies. It selects multiple initial tiles and generates se v eral mapping options, ultimately choosing the best one based on the number of free neighboring tiles for each core. CHMAP [12] calculates a priority v alue for each core based on its communication requirements and its position within a communication spanning tree. The algorithm then determines the mapping order and assigns cores to appro- priate tiles according to these computed priorities. On yx [13] proposed in 2009, introduces a lozenge-shaped mapping path and denes four mo v ement patterns to assign priorities t o tiles. This method has sho wn impro v ed communication cost compared to earlier heuristics. Spiral [14] starts by mapping the highest-priority task at the center of the mesh, then progressi v ely maps remaining tasks outw ard in a spiral pattern from already mapped cores. T o address hierarchical communication, V -CastNet3D is proposed in [15], a clustering-based mapping algorithm. Cores are grouped into clusters to reduce inter -cluster communication and the CastNet heuristic is then applied within each cluster for mapping onto a 2D NoC mesh. F or 3D meshes, certain techniques de- v eloped for 2D meshes ha v e been adapted. F or e xample, NMAP 3D, ILP3D, and PSMAP3D. Furthermore, CastNet3D [8] e xtends this approach to 3D NoC architectures by optimizing the utilization of v ertical links, thereby impro ving communication ef cienc y and reducing ener gy consumption. Due to the high computational cost of e xact methods and the limit ations of current processing capa- bilities, the third cate gory reli es on metaheuristic techniques, which ha v e emer ged as practical and scalable alternati v es for addressing the IP mapping problem in NoC architectures. Dra wing inspiration from natu- ral and biological phenomena, these approaches aim to ef ciently e xplore lar ge sol ution spaces and produce near -optimal solutions within reasonable computational time. In the conte xt of 2D NoC architectures, se v eral metaheuristic techniques ha v e been proposed. In [16], the authors proposed CGMAP , a genetic algorithm- based approach that replaced the traditional random initialization with a chaotic mapping operator , enhancing the e xploration capabilities of the algorithm. GBMAP [17] emplo ys an e v olutionary algorithm to ef ciently map processing cores onto NoC tiles . Sw arm intelligence-based approaches ha v e also been e xplored. F or e x- ample, a discrete particle sw arm optimization (PSO) method is proposed in [18], utilizing deterministic initial solutions to impro v e performance. The same authors proposed se v eral metaheuristic-based mappi ng techniques using PSO, ant colon y optimization (A CO), articial bee colon y (ABC), and dif ferential e v olution (DE). These approaches aim to optimize task mapping in NoC architectures by reducing communication cost optimization in 2D NoC mapping problems. While these techniques are primaril y applied to 2D NoCs, recent research has e xtended m etaheuris- tic strate gies to 3D NoC architectures: in [19], a PSO-based algorithm is de v eloped for mapping IPs onto a partially v ertically-connected 3D mesh NoC. A PSO based mapping met h od is introduced in [18] to impro v e communication costs by applying bandwidth limitation. A similar approach is adopted in [20], b ut with the objecti v e of minimizing ener gy consumption. In [19], a quantum PSO to the 3D NoC mapping problem s proposed, thereby reducing po wer consumption. An adapti v e genetic algorithm based on logistic functions (LF A GA) is proposed in [21] to optimize the ener gy consumption of the netw ork. An ABC-based method for 3D NoC mapping is introduced in [22], demonstrat ing impro v ed results in communication optimization. A thermal-a w are mapping technique is proposed in [23], which i nte grates genetic algorithms with fuzzy logic to minimize the peak temperature in 3D NoC systems. Finally , the same authors proposed a simulated annealing (SA)-based approach to impro v e communication ef cienc y in 3D NoC application mapping. 4. MODDELING PLA CEMENT PR OBLEM In the conte xt of IP placement for NoC, the application is typically modeled as an IP core graph, while the NoC infrastructure is represented as a topology graph. The IP placement problem consists of assigning Int J Recongurable & Embedded Syst, V ol. 15, No. 2, July 2026: 373–385 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 377 logical IP cores dened by specic communication relationships and bandwidth demands within the IP core graph to ph ysical resource nodes in the NoC topology graph [5]. - NoC topology graph: the NoC topology is abstracted as a directed graph T ( R , L ) , where: R is the set of nodes, with each node r k ∈ R representing a tile in the NoC. L is the set of directed edges, where each edge l k ,l ∈ L represents a ph ysical communication link between tiles r k and r l [4]. - IP core graph: similarly to NoC topology , the IP core graph is a high le v el abstraction that represents the beha vior of an application. It is denoted as a directed graph G ( C , A ) , where: C is the set of nodes , each node c i ∈ C representing an IP core and A is the set of directed edges, where each edge a i,j ∈ A represents communication from IP source core c j to destination core c i [5]. Each edge a i,j ∈ A is associated with a weight w i,j which denotes the bandwidth requirement between the IPs c j and c i . - Placement function in NoC: the placement function denes the placement of IP cores from the IP core graph G ( C , A ) to nodes in the NoC topology graph T ( R , L ) , with the objecti v e of minimizing communication ener gy [13]. F or each IP core c i ∈ C , there e xists a corresponding node r k ∈ R in the NoC topology such that: map : V → T map ( c i = r k ) , ∀ c i ∈ C ∃ r j ∈ R . Furthermore, each IP core m ust be mapped to a unique node, ensuring that for an y tw o distinct IPs c i and c j : map ( c i ) ̸ = map ( c j ) . T o satisfy this constraint, the number of nodes in the NoC topology graph must be greater than or equal to the number of nodes in the IP core graph. If necessary , dummy nodes can be added to t he IP core graph to equalize the si zes of both graphs [3]. These dummy nodes are non communicating placeholders and do not participate in an y data e xchanges. - Solution repr ´ esentation: the solution is represented as a sequence with a permutation of the inte gers from 1 to n, where n is the number of nodes in the NoC topology graph [5]. Each position in the sequence corresponds to a node in the NoC topology . The v alue at that position indicates the ID of the IP core mapped to that node. An e xample of placement solution is illustrated in T able 1. T able 1. Solution e x emple Core number 1 2 3 4 5 6 7 8 9 Node place 8 3 2 1 9 5 6 7 4 - Objecti v e function: the objecti v e function used in this paper aims to minimize communication cost by reduc- ing the number of hops between tasks ma pp e d onto the NoC. The total communication cost is calculated as (1) [4]: commcost = X i X j w i,j ∗ nbhops ( r k , r l ) , (1) where c i = sour ce , c j = distination , map ( c i ) = r k , map ( c j ) = r l , c i ̸ = c j , and r k ̸ = r l . nbhopt ( . ) is the number of hops between the source and destination, calculated using the Manhattan distance, dened by (2): H ops ( r k , r l ) = | X k − X l | + | Y k − Y l | + | Z k − Z l | (2) where ( X k , Y k , Z k ) and ( X l , Y l , Z l ) are the coordinates of the nodes r k and r l on a 3D mesh NoC, respec- ti v ely . In the case of a 2D mesh NoC, Z k and Z l are equal to 0 . 5. PLA CEMENT WITH CR O W SEARCH ALGORITHM 5.1. Cr o w in natur e Cro ws are among the most intelligent animals in the animal kingdom. Biologists state that the y ha v e the most de v eloped brains of all birds, with intelligence comparable to that of a child aged 2 to 5 years. In the wild, researchers ha v e observ ed comple x beha viors such as the use of tools lik e sticks to achie v e goals, or e v en dropping stones on intruders approaching their nests [24]. Cr o ws are a lso kno wn for their c u nni ng. When hiding food while being w a tched by another cro w , the y may pretend to hide it in one place, then actually hide it some where else to decei v e the observ er . Unlik e most birds that rely mainly on v ocal sounds to communicate, cro ws also use sophisticated non-v ocal gestures a form of body language similar to sign language to con v e y more comple x information. The y are highly adaptable. The y can li v e in a wide v ariety of en vironments, from Cr ow sear c h algorithm for ef cient IP placement in 2D and 3D network-on-c hip ... (Maamar Bougher ar a) Evaluation Warning : The document was created with Spire.PDF for Python.
378 ❒ ISSN: 2089-4864 sno w and deserts to forests and mountains. Their omni v orous diet allo ws them to eat a broad range of food sources: meat, sh, fruits, seeds, carcasses, and e v en g arbage [25]. Due to its ef fecti v e balance between e xploration and e xploitation, achie v ed through its memory-based search mechanism and a w areness probability strate gy , and compared to traditional approaches such as the ge- netic algorithm, it requires fe wer control parameters and demonstrates strong performance in solving comple x combinatorial optimization problems [25]. Therefore, it is adopted in this w ork for the rst time to address the NoC mapping problem. 5.2. Cr o w sear ch algorithm steps The CSA is an optimization technique inspired by the intelligent beha vior of cro ws. In nature, cro ws hide e xcess food in dif ferent locations and retrie v e it when needed. The y are opportunistic and may follo w each other to nd better food sources. Ho we v er , if a cro w reali zes it is being follo wed, it may decei v e the other by mo ving to a f alse location [25]. In CSA, the search space represents the en vironment, and each cro w’ s position corresponds to a po- tential solution. The objecti v e function e v aluates the quality of the solution, similar to ho w food quality is assessed. The algorithm aims to nd t he global optimum—the best food source—by mimicking the cro ws’ strate gies of memory , deception, and e xploration. CSA models the social beha vior of cro ws using the follo w- ing assumptions [24]. - Cro ws li v e in ocks and interact socially . - Each cro w remembers the best position it has found (its hiding spot). - Cro ws follo w others in the sw arm to nd better solutions. - A cro w can decei v e another if it detects being follo wed, leading the follo wer to a random posit ion instead of its true hiding place. Consider a d dimensional search space represented by a number of cro ws. The total number of cro ws (ock size) is denoted by N . The position of cro w i at iteration iter is represented by a v ector in this d-dimensional space [26]. X i,iter = [ x i 1 , x i 2 , x i 3 . . . x i d ] (3) Each cro w i is equipped with a memory that stores the location of its personal hiding place m i . At iter - ation iter , this hiding place corresponds to the bes t position found by cro w i while e xploring the en vironment in search of better food sources (hiding places). Suppose that at iteration iter , cro w j intends to vis it its hiding place m j . At the same time, cro w i chooses to follo w cro w j in an attempt to approach its hiding place. In this conte xt, tw o possible scenarios may occur: - Cro w j is not a w are that it is being follo wed by cro w i . Consequently , cro w i mo v es closer to cro w’ s j hiding place. The ne w position of cro w i is then calculated as (4) [27]: X i,iter +1 = X i, iter + r i · f l i, iter · m j , iter − X i, iter (4) where m j , iter is the memory of the cro w j and f l is the ight length. - Cro w j is a w are that cro w i is follo wing it. Consequently , to protect its hiding place from being disco v ered, cro w j attempts to decei v e cro w i by mo ving to a dif ferent location within the search space, generating a feasible random solution [26]. The tw o scenarios described abo v e can be e xpressed in (5) [28]: X i,iter +1 = ( X i, iter + r i · f l i, iter · m j , iter − x i, iter if r j ≥ AP i,iter a r andom position other w ise (5) According to the equation, tw o k e y parameters play a crucial role in guiding the search process to w ard the global optimum: ight length and a w areness probability . These tw o parameters signicantly inuence the performance of the algorithm. Proper tuning ensures better results, as the y control the balance between intensication (e xploitation of good solutions) and di v ersication (e xploration of ne w re gions in the search space). Int J Recongurable & Embedded Syst, V ol. 15, No. 2, July 2026: 373–385 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 379 a. Flight length: the ight length ( f l ) parameter plays a crucial role in controlling the balance between e xplo- ration and e xploitation in the CSA. Small f l v alues promote local search beha vior , where the ne w position of a cro w remains close to either its current location or the memory of the cro w it follo ws [27]. This be- ha vior enhances solution renement within a limited re gion of the search space. In contrast, lar ge f l v alues encourage global search by allo wi ng the cro w to mo v e f arther from its current or tar get memory position, thus enabling the e xploration of pre viously un visited areas. b . A w areness probability: the a w areness probability ( AP ) controls also the balance between e xploitation and e xploration in the CSA. Lo w AP v alues promote e xploitation by allo wing follo wers to reach good solutions without being misled, while high AP v alues enhance e xploration by causing leaders to decei v e follo wers through random mo v ements. Therefore, careful tuning of AP is crucial to achie v e an ef fecti v e search balance [26]. The Algorithm 1 summarizes the main steps of the proposed approach, pro viding a clear o v ervie w of its operational o w [24]. Algorithm 1. The cro w search algorithm generate the population of the crow (the flock of crow) evaluate each crow with the objective function initialize the memory of each crow iter ← 0 while iter < max of iteration do for each crow i do Randomly choose one of the crows to follow j Define an awareness probability AP i Update position of the crow i using (5) Check the feasibility of new positions Evaluate the new position of the crows Update the memory of the crow end for iter ← iter + 1 end while return best solution 5.3. Modeling cr o w sear ch algorithm f or placement pr oblem In order to model the CSA so that it can ef fecti v ely address the placement problem, we ha v e deta iled its steps by aligning them with the specic requirements of the problem. - Step 1. Initialize the problem and algorithm parameters: at this stage, we dene the parameters required to properly calibrate the algorithm in order to obtain optimal results. This includes specifying the optimization problem, the objecti v e function and an y constraints and setting the k e y parameters of the CSA. - N : number of cro ws (population size), - maxt iter : maximum number of iterations, - f l : ight length (step size), - AP : a w areness probability . - Step 2. Initialize the positions and memories of t he cro ws: randomly position N cro ws in a d-dimensional search space, where each cro w represents a feasible solution to the placement problem. Each cro w has a memory in which it stores its best found position (initially set to its current position, as the cro w has no e xperience at iteration 0). - Step 3. Ev aluate initial tness: for each cro w , e v aluate the quality of its current position by inserting the corresponding decision v ariable v alues into the objecti v e function. - Step 4. Generate ne w positions: each cro w attempts to generate a ne w position in the s earch space. T o do so, cro w i randomly selects another cro w j and tries to mo v e to w ard cro w j’ s hiding place. This ne w position is calculated using (5) and this process is repeated for all cro ws. - Step 5. Check feasibility of ne w positions: for each cro w , the feasibility of the ne w generated position is e v aluated based on the problem’ s constraints. If the position is v alid, the cro w updates its current position to the ne w one. Otherwise, it remains at its current location without making an y changes. Cr ow sear c h algorithm for ef cient IP placement in 2D and 3D network-on-c hip ... (Maamar Bougher ar a) Evaluation Warning : The document was created with Spire.PDF for Python.
380 ❒ ISSN: 2089-4864 - Step 6. Update memory: the cro ws update their memory according to (6). m i, iter +1 = ( X i, iter +1 if f ( X i, iter +1 ) < f ( m i, iter ) m i, iter otherwise (6) In other w ords, if the ne w position of cro w i yields a better tness v alue than the one currently stored in its memory , the memory is updated with the ne w position. Otherwise, it remains unchanged. - Step 7. Check stopping criterion: the loop comprising steps 4 to 7 is repeated unt il the predened maximum number of iterations (iter max ) is reached. Once the stoppi ng criterion is met, the best solution stored in memory (in ter ms of the objecti v e function v alue) is returned as the nal solution to the optimization problem. 6. EXPERIMENT RESUL T T o assess the ef fecti v eness of the placement approach in a NoC architecture, a range of benchmarks is typically emplo yed [13]. These benchmarks comprise interconnected tasks that mimic the beha vior of real- w orld applications. Each task models a processing unit, along with the communication links between them, enabling the analysis of critical architectural characteristics such as ener gy consumption and communication o v erhead. In this w ork, we consider tw o main types of benchmarks: a. Synthetic benchmarks: these benchmarks are generated automatically using the task graphs for free (TGFF) tool [29], which enables the creation of di v erse task graphs with customizable parameters such as the number of tasks, communication v olume, and e x ecution tim e. Synthetic benchmarks are especially v aluable for testing NoC architectures across a wide range of controlled and v aried scenarios. b . Real-w orld benchmarks: these benchmarks are e xt racted from practical multimedia applications and are widely used to e v aluate NoC architectures. Figure 3 sho wcases four representati v e e xamples from this cate gory: - V OPD is a decoding application deri v ed from MPEG-4 that processes video object planes (Figure 3(a)). - MPEG-4 is an object-based video compression standard that enables ef cient parallel processing of multi- media data (Figure 3(b)). - PIP represents a sequence of image processing stages used to e v aluate pipelined e x ecution and parallelism (Figure 3(c)). - MWD m o de ls realistic multimedia w orkloads, including audio and video processing tasks, to assess system performance under comple x and heterogeneous applications (Figure 3(d)). Figure 3. Benchmarks used in the e xperiments: (a) video object plane decoder (V OPD), (b) mo ving picture e xperts group (MPEG4), (c) picture in picture (PIP), and (d) multi-windo w display (MWD) The benchmarks V OPD, MPEG4, PIP , and MWD are commonly used to e v aluate NoC architectures. V OPD and MWD represent video decoding and signal-processing tasks with intensi v e inte r -core communica- tion, while MPEG4 simulates video compression w orkloads and PIP handles multiple video streams simulta- neously . T ogether , the y pro vide realistic and di v erse communication patterns for testing NoC performance. 6.1. Setting Before presenting the e xperimental results, we rst detail the conguration parameters used in our study . F or the real w orld benchmarks, the V OPD, MPEG4, and MWD applications were mapped onto a 4×4 Int J Recongurable & Embedded Syst, V ol. 15, No. 2, July 2026: 373–385 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 381 in 2D NoC and a 2×4×2 in 3D architecture. As for the PIP benchmark, due to its smaller task graph, it w as mapped to a 2×2×2 3D topology . Re g arding the synthetic benchmarks, six benchemarks are used from [30], we emplo yed a 2D mesh NoC with a symmet ric conguration ( x = y ), as well as a 3D mesh NoC with full symmetry in all dimensions ( x = y = z ). T o calibrate the right parameters of the algorithm, man y tests are e x ecuted v arying the population size is setted to 500 and the maximum number of iterations is 1000. As highlighted befor , the ight length ( f l ) is a critical parameter that signicantly inuences the performance of the algorithm. T o ensure a balanced trade-of f between e xploration and e xploitation capabilities, we considered tw o scenarios: one with f l < 1 and another with f l > 1 . This choice enables the algorithm to ef f ecti v ely capture both global search (e xploration) and local renement (e xploitation) beha viors. The f l parameter w as set to f L < 1 = 0 . 2 and f L > 1 = 2 , Ho we v er , both r and AP are randomly generated in the interv al [0 , 1] for each cro w and at e v ery iteration, introducing dynamic v ariability in the search process. 6.2. Result and discussion T able 2 presents the performance e v aluation of the CSA placement approach under tw o congurations dened by the f l parameter , for both 2D and 3D NoC topologies across all selected benchmarks. The obtained v alues correspond to the communication cost, which is considered as the objecti v e function to be minimized in this paper . T able 2. Comparison of obtained result with f l Benchmarks # T ask # Edge f l < 1 f l > 1 CSA 2D CSA 3D CSA 2D CSA 3D TG0 12 13 24800 22100 24700 22000 TG1 16 16 35600 32400 36600 31700 TG2 27 27 88000 74000 87500 71800 TG3 30 34 113600 92000 113000 92000 TG4 50 59 260500 198400 253100 194500 TG5 62 70 363000 283700 384000 287300 The results clearly sho w that the 3D NoC conguration consistent ly outperforms the 2D design, un- derscoring the benets of le v eraging the third dimension the placement problem. This performance g ain is particularly e vident in both setups when applying the CSA algorithm, as reected by the f l v alue. By intro- ducing the e xtra dimension, 3D NoCs reduce communicati on distances, which translates into more ef cient resource utilization and o v erall better performance than 2D architectures. The visual representations in Figure 4 pro vide a comparati v e analysis of the placement outcomes obtained with CSA in both 2D and 3D NoC ar - chitectures, considering bo t h parameter v alues of the o w latenc y f actor ( f l ). Similarly , also e v aluated under the tw o f l parameter settings. T ogether , these analyses highlight the signicant impact of the f l f actor on the quality of task-to-core placement. TG0 TG1 TG2 TG3 TG4 TG5 TG0 TG1 TG2 TG3 TG4 TG5 0 100 , 000 200 , 000 300 , 000 400 , 000 24 , 700 36 , 600 87 , 500 1 . 13 · 10 5 2 . 53 · 10 5 3 . 84 · 10 5 22 , 000 31 , 700 71 , 800 92 , 000 1 . 95 · 10 5 2 . 87 · 10 5 24 , 800 35 , 600 88 , 000 1 . 14 · 10 5 2 . 61 · 10 5 3 . 63 · 10 5 22 , 100 32 , 400 74 , 000 92 , 000 1 . 98 · 10 5 2 . 84 · 10 5 NoC 2D NoC 3D Comm unication Cost > 1 < 1 Figure 4. Comparison between placement solution Cr ow sear c h algorithm for ef cient IP placement in 2D and 3D network-on-c hip ... (Maamar Bougher ar a) Evaluation Warning : The document was created with Spire.PDF for Python.
382 ❒ ISSN: 2089-4864 A close r e xamination of the results sho ws that when the o w latenc y f actor e xceeds one ( f l > 1 ), the outcomes systematically impro v e. As pre viously discussed, a smalle r v alue of f l f a v ors local search intensi - cation, whi le a lar ger v alue encourages di v ersication in the e xploration process. In our case, we observ ed that higher f l v alues consistently yield bet ter results compared to smaller ones, conrming that di v ersication in the search process leads to superior outcomes. Before comparing our CSA placement approach with e xisting methods from the literature, we rst e v aluate its ef fecti v eness by benchmarking it ag ainst e xtended algorithms proposed by the same authors for 3D NoC architectures, namely ABC and simulat ed annealing, and then com- pare the optimal results it produces with those obtained from other state-of-the-art approaches. T able 3 reports the outcomes related to the 2D and 3D NoC topology . T able 3. Comparison of obtained result in 2D and 3D Benchmarks 2 D 3 D SA ABC CSA SA ABC CSA TG0 32400 49300 24700 27800 31700 22000 TG1 39700 63400 36600 37200 40600 31700 TG2 94700 115100 87500 78000 73000 71800 TG3 - 179900 113000 - 121100 92000 TG4 - 326400 253100 - 199900 194500 TG5 - 419600 384000 - 273200 287300 Figure 5 illustrates the scalability of the proposed approaches with respect to the number of cores in both 2D and 3D NoC architectures. It sho ws the v ariation of the objecti v e function v alues obtained by the tw o proposed algorithm v ersions and the ABC algorithm, highlighting their comparati v e performance under dif ferent netw ork sizes. The results presented in the F igures 5(a) and 5(b) indicate that the proposed v ersions generally achie v e better objecti v e function v alues as the number of cores increases. Ho we v er , in the 3D NoC architecture, the ABC algorithm tends to perform better for lar ger numbers of cores. T able 4 presents the results related including a comparati v e analysis with other placement methods from the literature related to 2D and 3D NoC. 10 15 20 25 30 35 40 45 50 55 60 65 100 , 000 200 , 000 300 , 000 400 , 000 Num b er of Cores Ob j e ctiv e F unction V alue ABC CSA > 1 CSA < 1 (a) 10 15 20 25 30 35 40 45 50 55 60 65 50 , 000 100 , 000 150 , 000 200 , 000 250 , 000 300 , 000 Num b er of Cores Ob j e ctiv e F unction V alue ABC CSA > 1 CSA < 1 (b) Figure 5. Scalability results: (a) 2D and (b) 3D The comparison on real benchmarks indicates that the CSA deli v ered superior results for the V OPD application in 3D. Ho we v er , for the remaining benchmarks, the performance e xhi b i ted certain limitations. These shortcomings can be lar gel y attrib uted to the use of a uniform, generalized conguration applied across all benchmarks, without adjusting the parameters to the specic characteristics of each case. Notably , the num- ber of iterations w as x ed at 1000 for all e xperiments and population s ize w as 500 , which may not ha v e been suf cient or optimal for e v ery benchmark. This observ ation highlights the importance of adapti v e parameter tuning particularly with respect to iteration count and population size which could signicantly enhance the algorithm’ s performance and lead to more consistent impro v ements across di v erse applications. Int J Recongurable & Embedded Syst, V ol. 15, No. 2, July 2026: 373–385 Evaluation Warning : The document was created with Spire.PDF for Python.