Rateless Codes Design Scheme Based on Two Stages

Abstract

Current rateless codes coding schemes ignored the order recovery of packets. To cope with this problem, average delay and maximum memory consumption were proposed as performance indices to characterize the order recovery performance, then a coding scheme based on two stages coding was proposed to improve the order recovery performance. Encoding of the front k coded symbols is the first stage, which the ith coded symbol is compose of the ith packet and other di-1 packets which are chosen from the front i-1 packets with equal probability. Encoding of the remaining infinite coded symbols is the second stage which the packets are chosen from all packets equal probably. The simulation results show that the rateless codes from the proposed scheme have better order recovery performance, meanwhile have high bandwidth efficiency and good uniformity recovery than LT codes.