Optimized ultra-low power and reduced delay GNR Ternary SRAM using a 7-transistor architecture

Abstract

Greater need and evolution in electronics require a memory device that can go with a decreased power delay, SRAM plays an important role as a storage element in digital circuit design. Power and delay are vital problems faced by today’s RAM technology. It is necessary to lessen the power and increase the speed. There is a need to reduce power utilization and time delay. The proposed method is seen in the Electronics technical tool H-Spice technology. The technique proposed on DRG 7T- transistors SRAM consumes less power and delay. After the analysis and enhancement of the circuit, this approach gives the power delay product of the graphene nanoribbon (GNR) 7T SRAM as 80% at 0.7 V, 59% at 0.8 V, 34 % at 0.9 V, which is much less when compared to conventional SRAM power delay product.