Effective ethernet controller protocol architecture verification strategy using system Verilog

Abstract

The pre-silicon verification is typically more significant than post-silicon verification, which produces an algorithm with the correct functionality and timing parameters. In this paper we propose innovative pre-silicon verification methodology focused on the Ethernet controller architecture as the design under test (DUT). The methodology employs a layered verification architecture implemented using the system Verilog language, aiming to streamline the testing process. A novel test pattern test generator, interfaces and blocks are used to perform the verification. The test patterns are generated based on the operational principles of the ethernet controller block, ensuring comprehensive verification coverage. Additionally, the paper combines different verification parameters with existing approaches to demonstrate the effectiveness of the proposed methodology. It is observed that the performance of the proposed method is better compared to existing methods.