System-on-chip design for improved switching angle driven 35-level LUO progression-based multi-level inverter

Abstract

This article concentrates on the development of the IC layout for the driving switches of the inverter with improved switching control. This work uses the improved non-carrier switching pattern algorithms to have precise control of inverter switches with twin objectives of i) reducing the total harmonic distortion (THD)% and ii) developing a dedicated system on chip for the improved switching control of the 35-level switched ladder multi-level inverter. The DC voltage of the inputs to the inverter is designated based on the LUO progression, which consists of an improved mathematical formula for deriving its values. Conventionally, the multi-level inverter circuits are driven by the pulse width modulation signals by overlapping the modulating sine wave with different levels of triangle waves, such as phase disposition, phase opposite disposition, and alternate phase opposite disposition, utilized to drive various voltage source inverter topologies. Although the MLI design concentrates on minimal THD%, factors like accuracy, minimum number of switches, and cost demands for advanced switching strategy algorithms. This paper compares the improved switching angle method to the existing algorithm by considering VPEAK, VRMS, and %THD for the 35-level LUO progression-based switched ladder inverter. The IC layout for the improved switching control is developed using the hardware description language code in the Cadence tool and validated by cross-compiling in Simulink MATLAB.