Efficient design of approximate carry-based sum calculating full adders for error-tolerant applications

Abstract

Approximate computing is an innovative circuit design approach which can be applied in error-tolerant applications. This strategy introduces errors in computation to reduce an area and delay. The major power-consuming elements of full adder are XOR, AND, and OR operations. The sum computation in a conventional full adder is modified to produce an approximate sum which is calculated based on carry term. The major advantage of a proposed adder is the approximation error does not propagate to the next stages due to the error only in the sum term. The proposed adder was coded in verilog HDL and verified for different bit sizes. Results show that the proposed adder reduces hardware complexity with delay requirements.