Crow search algorithm for efficient IP placement in 2D and 3D network-on-chip architectures

Abstract

The communication in system-on-chip (SoC) has evolved to meet the increas-ingly complex requirements of modern applications. To address connectivity challenges, the network-on-chip (NoC) has emerged as an efficient solution. While traditional NoCs are primarily based on 2D architectures, the inherent limitations of 2D designs have driven the adoption of 3D architectures, which offer enhanced space utilization and performance optimization. A key step in the design of NoC systems is the placement of cores, also known as the map-ping phase, in which application tasks are assigned to the architecture’s process-ing elements. This phase is considered an nondeterministic polynomial (NP)-complete problem due to its combinatorial complexity. Optimizing this phase is crucial, as it directly impacts the overall performance of the NoC. Various opti-mization algorithms have been employed to maximize the efficiency of 2D and 3D NoCs. In this paper, we adopt the crow search algorithm to find the places both 2D and 3D NoCs with minimal comunication. The goal is to evaluate its performance compared to other optimization algorithms in this crucial step.