Flicker noise suppression and tuning range linearization techniques for RF CMOS voltage-controlled oscillators

Abstract

This paper proposes a differential RF CMOS voltage-controlled oscillator (VCO) employing a series LC (SLC) network to suppress 1/f³ flicker noise and linearize the tuning range. The SLC network incorporates two coupling capacitors connected to each node of a parallel inductor-varactor tank. Each series connection node is cross-coupled to the gates of switching transistors, facilitating a large signal swing. By optimizing the coupling capacitance, 1/f³ flicker noise is effectively mitigated. Designed in 180 nm CMOS technology, the proposed NMOS-only SLC VCO is compared with a conventional differential VCO using a parallel LC (PLC) network. Targeted for 3.3 GHz applications, the VCO maintains a consistent phase noise slope of −20 dB/decade across offset frequencies from 1kHz to 10 MHz. The SLC VCO achieves a phase noise of −71.6 dBc/Hz at a 1 kHz offset and −131.5 dBc/Hz at a 1 MHz offset with a power consumption of 11.9 mW from a 1.5 V supply. The resulting figure of merit (FOM) is 191.3 dBc/Hz at a 1 MHz offset.