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29,922 Article Results

Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

10.11591/ijres.v8.i3.pp194-205
Amanpreet Sandhu , Sheifali Gupta
Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.
Volume: 8
Issue: 3
Page: 194-205
Publish at: 2021-02-22

A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

10.11591/ijres.v8.i3.pp162-168
Pritty Pritty , Manoj Kumar , Mariyam Zunairah
Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.
Volume: 8
Issue: 3
Page: 162-168
Publish at: 2021-02-22

Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder

10.11591/ijres.v8.i3.pp185-193
N. Saravanakumar , K. Sakthi Sudhan , K. N. Vijeyakumar , S. Saranya
This paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.
Volume: 8
Issue: 3
Page: 185-193
Publish at: 2021-02-22

Designing ALU using GDI method

10.11591/ijres.v8.i3.pp151-161
Mohammadreza Fadaei
As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.
Volume: 8
Issue: 3
Page: 151-161
Publish at: 2021-02-22

Design and implementation of CNTFET based ternary 1x1 memories

10.11591/ijres.v8.i3.pp175-184
S.Tamil Selvan , M. Sundararajan
In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.
Volume: 8
Issue: 3
Page: 175-184
Publish at: 2021-02-22

512 bit-SHA3 design approach and implementation on field programmable gate arrays

10.11591/ijres.v8.i3.pp169-174
S. Neelima , R. Brindha
In this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1.
Volume: 8
Issue: 3
Page: 169-174
Publish at: 2021-02-22

Bangla language textual image description by hybrid neural network model

10.11591/ijeecs.v21.i2.pp757-767
Md. Asifuzzaman Jishan , Khan Raqib Mahmud , Abul Kalam Al Azad , Mohammad Rifat Ahmmad Rashid , Bijan Paul , Md. Shahabub Alam
Automatic image captioning task in different language is a challenging task which has not been well investigated yet due to the lack of dataset and effective models. It also requires good understanding of scene and contextual embedding for robust semantic interpretation of images for natural language image descriptor. To generate image descriptor in Bangla, we created a new Bangla dataset of images paired with target language label, named as Bangla Natural Language Image to Text (BNLIT) dataset. To deal with the image understanding, we propose a hybrid encoder-decoder model based on encoder-decoder architecture and the model is evaluated on our newly created dataset. This proposed approach achieves significance performance improvement on task of semantic retrieval of images. Our hybrid model uses the Convolutional Neural Network as an encoder whereas the Bidirectional Long Short Term Memory is used for the sentence representation that decreases the computational complexities without trading off the exactness of the descriptor. The model yielded benchmark accuracy in recovering Bangla natural language and we also conducted a thorough numerical analysis of the model performance on the BNLIT dataset.
Volume: 21
Issue: 2
Page: 757-767
Publish at: 2021-02-01

Stochastic local search: a state-of-the-art review

10.11591/ijece.v11i1.pp716-727
Muhamet Kastrati , Marenglen Biba
The main objective of this paper is to provide a state-of-the-art review, analyze and discuss stochastic local search techniques used for solving hard combinatorial problems. It begins with a short introduction, motivation and some basic notation on combinatorial problems, search paradigms and other relevant features of searching techniques as needed for background. In the following a brief overview of the stochastic local search methods along with an analysis of the state-of-the-art stochastic local search algorithms is given. Finally, the last part of the paper present and discuss some of the most latest trends in application of stochastic local search algorithms in machine learning, data mining and some other areas of science and engineering. We conclude with a discussion on capabilities and limitations of stochastic local search algorithms.
Volume: 11
Issue: 1
Page: 716-727
Publish at: 2021-02-01

On the dispatch of minigrids with large penetration levels of variable renewable energy

10.11591/ijeecs.v21.i2.pp673-681
Anan A. Dweekat , Mohamed Shaaban , Sze Song Ngu
The continuous use of fossil fuels for decades in electricity generation has led to dire environmental consequences. This has fostered the incorporation of variable renewable energy resources (RES) to improve the environmental outlook and minimize emissions. This paper presents an approach for the dispatch of a minigrid considering variable solar photovoltaic (PV) generation. Due to the variability of the solar irradiance received from the sun during daytime only, solar irradiance is modeled as a stochastic random variable that is fitted into a Beta probability density function (PDF). The minigrid dispatch problem, modeled using stochastic optimization, is then approximated into a linear equivalent to become a mixed integer linear programming (MILP) problem that can be solved efficiently. The proposed approach is implemented on the modified IEEE 14-bus test system to verify its capability in solving the minigrid dispatch under various test case scenarios.  
Volume: 21
Issue: 2
Page: 673-681
Publish at: 2021-02-01

Modified artificial bee colony optimization algorithm for adaptive power scheduling in an isolated system

10.11591/ijeecs.v21.i2.pp1168-1175
Vijo M. Joy , S. Krishnakumar
The objective of this work is to solve the power scheduling problems for efficient energy management by assigning the optimal values. Artificial neural networks are used widely in the field of energy management and load scheduling. The  backpropagation technique is used for the feed-forward neural network training and the Levenberg-Marquardt algorithm is used to minimize the errors. The slow speed of convergence and getting stuck in local minima are some negatives of   backpropagation in complex computation. To overcome these drawbacks an innovative meta-heuristicsearch algorithm called modified artificial bee colony optimization algorithm is used. A hybrid neural network is introduced in this work.  The simulation result shows that the efficiency of the systemis improved when hybrid optimization is used. With this method, the system achieves an optimalaccuracy of 99.23%
Volume: 21
Issue: 2
Page: 1168-1175
Publish at: 2021-02-01

Performance comparison of hybrid active power filter for p-q theory and SVPWM technique

10.11591/ijece.v11i1.pp84-93
T. M. Thamizh Thentral , K. Vijayakumar , R. Jegatheesan
Harmonic Distortion in many of the industrial applications are occur primarily owing to the enormous utilization of loads with high non-linearity like power converters, speed varying drives and arc furnaces. The power semiconductor is used to achieve the variation in speed and conversion from one source to another. Mostly active filters and tuned filters are utilized to remove the harmonic included in the source current. The tuned passive filters and inductance inserted in the line reduces the harmonics but at the same time induces the resonances in most of the industrial applications. Due to this, harmonic distortion increases in the source current and voltage. This can be reduced by adding hybrid filter in the system with decreased rating of active filter in high power applications. This article deals with the various topology of hybrid filters. The working of the proposed filter design in variable inductance mode based on the pollution created in the source voltage and current is studied. In the proposed hybrid filter passive filter is tuned with seventh harmonic frequency and connected in series with active filters to reduce the harmonic distortion. DC link voltage and the active filter VA rating could be minimized. The control signal to the filter is derived from p-q theory and space vector pulse width modulation (SVPWM). The performance of the system under study is simulated and noted for the THD percentage before and after the filter is added to the system and the same model is experimented with reduced voltage level.
Volume: 11
Issue: 1
Page: 84-93
Publish at: 2021-02-01

Working memory enhancement during early childhood based on the utilization of interactive gesture game-based learning technique

10.11591/ijeecs.v21.i2.pp768-775
D. Lakshmi , Ponnusamy Ponnusamy
The use of human computer interaction is considered to be the most culturally and socially meritorious for the learning and playing activities of children. In this paper, a human interaction recognition system (HIRS) that includes gesture game-based learning is investigated for identifying its suitability and applicability in stimulation of working memory and primitive mathematical skills among the children in the early childhood period that ranges from 5 and 8 years.  In the proposed human interaction recognition system, the hand gestures are facilitated by the user for the objective of controlling the computer system based on the information extracted from the user gestures.This proposed research was implemented in three phases using a quasi-experimental design that in turn incorporates pre-test and post-test for investigating the behavior of experimental and control group considered from the respondents. In the first phase, the initial evaluation of the learner’s skill is achieved. The second phase used the developed technology in order to identify diversified parameters in different dimensions that contribute towards the assessment of working memory and primitive mathematical capabilities. Finally, the third phase is responsible for actual evaluation. In the phases of evaluation, four working memory tests such as forward Corsi Blocking-Tapping test, backward Corsi Blocking-Tapping test, Forward Digit Span test and backwardDigit Span test was conducted. In addition, the evaluation was also conducted for assessing primitive mathematical skill of children using TEDI-MATH. The results confirmed that Gesture Interactive Game-Based Learning (GIGL) used by the children exhibited a predominant improvement in the working memory and primitive mathematical skills on par with their usual school activities.
Volume: 21
Issue: 2
Page: 768-775
Publish at: 2021-02-01

A pulse amplitude modulation scheme based on in-line semiconductor optical amplifiers (SOAs) for optical soliton systems

10.11591/ijeecs.v21.i2.pp1014-1021
Aadel M. Alatwi , Ahmed Nabih Zaki Rashed
The objective of this work is to simulate a pulse amplitude modulation (PAM) scheme based on in-line semiconductor optical amplifiers for optical soliton systems. The max. power for soliton systems, based on various bits/symbol PAM modulation schemes after a fiber length of 100 km, is simulated and clarified. In addition to the max. Q factor for soliton systems, PAM modulation schemes with various in-line SOA injection currents and a fiber length of 100 km are also simulated and demonstrated in the results. The total electrical power after photo-detectors for soliton systems, based on PAM modulation schemes with various in-line SOA injection currents and a fiber length of 100 km, is also simulated and clarified in the results. The study emphasizes that the higher the SOA injection current, the higher the electrical power and the lower the Q factor that can be achieved in the soliton system.
Volume: 21
Issue: 2
Page: 1014-1021
Publish at: 2021-02-01

Enhanced sunflower optimization for placement distributed generation in distribution system

10.11591/ijece.v11i1.pp107-113
Thuan Thanh Nguyen
Installation of distribution generation (DG) in the distribution system gains many technical benefits. To obtain more benefits, the location and size of DG must be selected with the appropriate values. This paper presents a method for optimizing location and size of DG in the distribution system based on enhanced sunflower optimization (ESFO) to minimize power loss of the system. In which, based on the operational mechanisms of the original sunflower optimization (SFO), a mutation technique is added for updating the best plant. The calculated results on the 33 nodes test system have shown that ESFO has proficiency for determining the best location and size of DG with higher quality than SFO. The compared results with the previous methods have also shown that ESFO outperforms to other methods in term of power loss reduction. As a result, ESFO is a reliable approach for the DG optimization problem.
Volume: 11
Issue: 1
Page: 107-113
Publish at: 2021-02-01

Demilitarized network to secure the data stored in industrial networks

10.11591/ijece.v11i1.pp611-619
José R. Nuñez Alvarez , Yelena Pérez Zamora , Israel Benítez Pina , Eliana Noriega Angarita
Currently, the data and variables of a control system are the most important elements to be safeguarded in an industrial network, so it is vitally important to ensure their safety. This paper presents the design and simulation of a demilitarized network (DMZ) using firewalls to control access to all the information that is stored in the servers of the industrial network of the Hermanos Díaz Refinery in Santiago de Cuba, Cuba. In addition, the characteristics, configurations, methods, and rules of DMZs and firewalls are shown, select the configuration with three multi-legged firewalls as the most appropriate for our application, since it allows efficient exchange of data guaranteeing security and avoiding the violation of the control system. Finally, the simulation of the proposed network is carried out.
Volume: 11
Issue: 1
Page: 611-619
Publish at: 2021-02-01
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