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27,762 Article Results

Mutual Coupling Reduction between Asymmetric Reflectarray Resonant Elements

10.11591/ijece.v8i3.pp1882-1886
M. Hashim Dahri , M. H. Jamaluddin , M. Inam , M. R. Kamarudin
A physically asymmetric reflectarray element has been proposed for wide band operations. The dual resonant response has been introduced by tilting one side of the square path element. The numerical results have been analyzed in the frequency band between 24GHz to 28GHz where a reflection phase range of more than 600° has been achieved. The proposed asymmetric element can produce mutual coupling with adjacent elements on a reflectarray. This effect has been monitored by placing the elements in a mirror configuration on the surface of reflectarray. The single unit cell element results have been compared with conventional 4 element unit cell and proposed mirroring element configuration. The proposed mirroring element technique can be used to design a broadband reflectarray for high gain applications.
Volume: 8
Issue: 3
Page: 1882-1886
Publish at: 2018-06-01

Artificial Intelligence Control Applied in Wind Energy Conversion System

10.11591/ijpeds.v9.i2.pp571-578
Arama Fatima Zohra , Bousserhane Ismail Khalil , Laribi Slimane , Sahli Youcef , Mazari Benyounes
The objective of this paper is to study the dynamic response of the wind energy conversion system (WECS) based on the Doubly Fed Induction Generator (DFIG). The DFIG rotor is connected to the grid via a converter. The active and reactive power control is realized by the DFIG rotor variables control, using the field oriented control (FOC). The vector control of DFIG is applied by the use of tow regulators PI and the neural network regulator (NN). The generator mathematical model is implemented in Matlab/ Simulink software to simulate a DFIG of 1.5 MW in order to show the efficiency of the performances and robustness of the studied control systems. The simulation obtained results shows that the robustness and response time of the neural network regulator is better than those obtained by the PI classical regulator.
Volume: 9
Issue: 2
Page: 571-578
Publish at: 2018-06-01

FPGA Implementation of High Speed Hardware Efficient Carry Select Adder

10.11591/ijres.v7.i1.pp43-47
Saravanakumar Saravanakumar , Vijeyakumar Vijeyakumar , Sakthisudhan Sakthisudhan
This paper presents a novel architecture for high speed and hardware efficient carry select  addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.
Volume: 7
Issue: 1
Page: 43-47
Publish at: 2018-05-30

Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator

10.11591/ijres.v7.i1.pp21-33
Sanket Dessai , Sandeep G.
This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.
Volume: 7
Issue: 1
Page: 21-33
Publish at: 2018-05-30

An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications

10.11591/ijres.v7.i1.pp12-20
Deepak Prasad , Vijay Nath
In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.
Volume: 7
Issue: 1
Page: 12-20
Publish at: 2018-05-30

Thermal Analysis of Fair Scheduling in Real-time Embedded Systems

10.11591/ijres.v7.i1.pp48-56
Tayyaba Bokhari , Sajjad Haider Shami , Farhan Haseeb
Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations.
Volume: 7
Issue: 1
Page: 48-56
Publish at: 2018-05-30

Universal Automobile Headlight Control Module for High Beam Adaptation during Night Vision Travel an Embedded Design Approach

10.11591/ijres.v7.i1.pp34-42
M. Subramania Siva , G. Jeyakumar
Road accidents during night travel increases day by day and vision impairment due to high beam contributes to the majority of the total fatalities. Headlights of vehicles pose a great danger during night driving. [1] The drivers of most vehicles use high/bright beam while driving at night. This causes a discomfort to the person travelling from the opposite direction. The driver experiences a sudden glare caused due to the high intense headlight beam from the other vehicle coming towards him from the opposite direction. We are expected to dim the headlight to avoid this glare. This glare causes a temporary blindness to a person resulting in road accidents during the night. To avoid such incidents, an embedded prototype of Automatic Headlight adaptor module is proposed. This embedded module automatically switches the high beam to low beam and returns backs to high beam, thus reducing the sudden glare effect. It also eliminates the requirement of manual switching by the driver to switch back to low beam Universal Headlight adaptor module is a unique solution to achieve the above objective, the headlight intensity of the incoming vehicles causing the glare is automatically attenuated to low beam wirelessly by the nearby vehicles affected by high beam. The interconnected modules at every vehicle independently takes the decision on the head light control of the source vehicle causing the glare by evaluating various parameters like vehicle speed, current GPS location, direction of vehicle etc.
Volume: 7
Issue: 1
Page: 34-42
Publish at: 2018-05-30

Application of Inverse Perspective Mapping for Advanced Driver Assistance Systems in Automotive Embedded Systems

10.11591/ijres.v6.i3.pp150-159
Vighnesh N.T , Rachana Anil , Rohith Kumar D , Sanjana Sharvana , Rajeshwari Hegde , B S Nagabhushana
In the recent times vehicle manufactures and automotive suppliers are progressing towards building vision based subsystems for provisioning driver assistance while targeting the automotive safety critical needs. While the acquired images constitute the fundamental input for any vision based system, transforms on images become essential to derive and gain insight into certain specific features. These derived features are used and reused at multiple places for varied automotive applications. This situation warrants a scalable and flexible image processing platform for a class of automotive applications. An attempt is made in this Research work to propose architecture that, specially, includes a layer of image transformations and to implement a prototype image processing platform. Inverse Perspective Mapping (IPM), a widely used class of transforms is emphasized in the present architecture alongside other nominal transforms. Lane departure warning system is implemented on this platform for the purpose of illustration and to analyze the effectiveness of the proposed architecture
Volume: 6
Issue: 3
Page: 150-159
Publish at: 2018-05-28

Smart Assisted Vehicle for Disabled/Elderly using Raspberry Pi

10.11591/ijres.v6.i2.pp82-87
Shubham Pandey , Shubham Chandewar , Krishnamoorthy A.
Independent mobility is a key component in maintaining the physical and psychosocial health of an individual. Further, for people e having disabled/elderly, independent mobility increases vocational and educational opportunities, reduces dependence on caregivers and family members, and promotes feelings of self-reliance. Psychologically, a decrease in mobility can lead to feelings of emotional loss, anxiety, depression, educed self-esteem, social isolation, stress, and fear of abandonment. Even though the benefits of powered mobility are well documented, the safety issues associated with operation of powered vehicles often prevent clinicians and rehabilitation practitioners from prescribing powered mobility. So we are introducing an intelligent vehicle for disables/elderly people which uses an array of sensors to help with the movement of the vehicle with minimal human interaction. Functionalities of the proposed system are further enhanced using android interface connect to the vehicle via Bluetooth.
Volume: 6
Issue: 2
Page: 82-87
Publish at: 2018-05-28

Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

10.11591/ijres.v6.i1.pp36-40
G. Vadiraj , K. Shivanand , B. Sampat , G. Subramanya Nayak
Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.
Volume: 6
Issue: 1
Page: 36-40
Publish at: 2018-05-28

Simulation and Real Time Implementation of Various PWM Strategies for 3 Φ Multilevel Inverter Using FPGA

10.11591/ijres.v6.i1.pp1-19
C. R. Balamurugan , S. P. Natarajan , T. S. Anandhi , B. Shanthi
For high power applications Multilevel Inverter (MLI) is extensively used. The major advantages of MLI are good power quality, low switching losses and maintenance of the desired voltage. In this work, the three phase cascaded multi level inverter is analyzed under various modulation techniques that include Sub-Harmonic Pulse Width Modulation (SHPWM) i.e. Phase Disposition (PD) strategy, Phase Opposition Disposition (POD) strategy, Alternate Phase Opposition Disposition (APOD) strategy, hybrid strategy (PD and PS) and Phase Shift (PS) strategy. The study will help to choose those techniques with reduced harmonics for the chosen three phase cascaded MLI with R-L load. The Total Harmonic Distortion (THD), VRMS (fundamental), crest factor and form factor are evaluated for various modulation indices at two different switching frequencies (3.15KHz and 6 KHz). Simulation is performed using MATLAB-SIMULINK. It is observed that HYBRID PWM and PSPWM methods provide output with relatively low distortion for low and high switching frequencies. PODPWM and PSPWM are found to perform better since they provide relatively higher fundamental RMS output voltage for 6 KHz and 3.15 KHz switching frequencies. The experimental result shows PSPWM provide output with low distortion and HYBRID PWM provide output with higher fundamental RMS voltage for fc=3.15KHz. The experimental results were obtained only for fc=3.15KHz.
Volume: 6
Issue: 1
Page: 1-19
Publish at: 2018-05-28

Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

10.11591/ijres.v6.i3.pp160-168
G. Prasad Acharya , M. Asha Rani
This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.
Volume: 6
Issue: 3
Page: 160-168
Publish at: 2018-05-28

Metal-Embedded SU-8 Slab Techniques for Low-Resistance Micromachined Inductors

10.11591/ijres.v6.i2.pp88-96
Manot Mapato , Prapong Klysuban , Thanatchai Kulworawanichpong , Nimit Chomnawang
This work presents new fabrication technique for micro power-inductors by using metal-embedded SU-8 slab techniques. This techniques used X-ray lithography to fabricate high aspect-ratio LIGA-like micro-structures in form of embedded structure in SU-8 slab and applied for inductor’s winding fabrication with aspect-ratio of 10. Thishigh-aspect ratiostructure can provide very low resistance winding but preserve small form factor and low profile. Inductors were designed as pot-core structures with8 μm-thick permalloy core and 250 μm-thick copper winding. 4-types of inductors were fabricated including 3, 5, 10 and 16 turns in the area of 1.8 mm2 to 9.5 mm2. All inductors have overall heights of 370 μm, measured inductance value in a range of 70 nH to 1.3 μH at 1 MHz and DC resistance value of 30 mΩ to 336 mΩ for 3 turns to 16 turns respectively. From this result, high aspect-ratio inductors show good results including low-resistance, high inductance, and a small form factor as expected. 
Volume: 6
Issue: 2
Page: 88-96
Publish at: 2018-05-28

On-chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices

10.11591/ijres.v6.i1.pp41-47
Anurag Shrivastava , Sudhir Kumar Sharma
Today’s scenario of SOC deals with integrity and sharing of information or data with various level of communication. AMBA bus protocol has been proposed by ARM community to justify the uneven demand of integrity .In this paper functional description and implementation of high peripheral devices supporting protocol AXI2.0 and its interface between low peripheral devices has been proposed. The connection named as bridge take care of the protocol mismatch and operates on data transfer for uneven speed demand. Asynchronous   FIFO has been considered to avoid the complex handshaking mechanism. The design has been implemented within VHDL and implemented on Xilinx Virtex 4.
Volume: 6
Issue: 1
Page: 41-47
Publish at: 2018-05-28

MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN

10.11591/ijres.v6.i2.pp120-126
Ramesh Pawase , N.P. Futane
Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed.  A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization.  The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.
Volume: 6
Issue: 2
Page: 120-126
Publish at: 2018-05-28
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