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28,451 Article Results

A Bandwidth Degradation Technique to Reduce Call Dropping Probability in Mobile Network Systems

10.11591/ijeecs.v16.i2.pp303-307
CH. Monica , K.V.L. Bhavani
A generic video telephony may require more than 40 kbps whereas a low motion video telephony may require about 25 kbps for data transmission. From the designing point of view these requirements demands for an alternative resource planning, especially for bandwidth allocation in wireless networks. In wireless network where bandwidth is a scare resource, the system may need to block incoming user if all of the bandwidth has been used to provide highest quality of service to existing users. However this bandwidth resource planning may be unacceptable for larger application. This work aims towards a realization of a mobile network using W-CDMA multi access technique supporting multilevel quality of services. The bandwidth allocation to multiple users is adjusted dynamically according to the required network condition so as to increase bandwidth utilization. The work analyzes the performance deriving the degradation period ratio, mean degradation time and degradation state for the implemented wireless network. The proposed work is aim to implement on Matlab tool for its functional verification considering various mobility patterns.
Volume: 16
Issue: 2
Page: 303-307
Publish at: 2015-11-01

Effects of Parameters Variation in Fuzzy based Induction Motor Drives

10.11591/ijeecs.v16.i2.pp272-280
Marizan Sulaiman , Zulhisyam Salleh , Rosli Omar
This paper presents the effects of parameters variation over the speed response of vector controlled induction motor drives for high performance applications. The design and simulation of fuzzy logic controller are considered based on design case constant parameter fuzzy logic (DCCPFL) controller. The scaling factors for DCCPFL controller are calculated based on identified motor parameter. The performance of the DCCPFL is compared with conventional PI controller. Three different parameters is tested under no-load and loaded conditions namely rotor resistance, inertia and self-inductance. From the simulation results, it is proved that the DCCPFL have better performance in term of different parameter variations and also load disturbances. Thus the DCCPFL is appropriate to replace the conventional PI for high performance of induction motor drives system.
Volume: 16
Issue: 2
Page: 272-280
Publish at: 2015-11-01

Study of Hybrid PV-Wind Energy System to Isolated Micro-grid

10.11591/ijeecs.v16.i2.pp221-231
Samir M. Dawoud , Xiangning Lin
The optimal sizing of the isolated hybrid microgrid using an optimization technique was proposed. The hybrid system features WT, PV and conversion systems were used to feed the electrical load demand. A HOMER software was used to model system performance during a time of one year, considering Sensitivity variations in both the availability of renewable energy sources and variations in the load demand. The optimal solution was obtained with respect to decrease the cost of energy (COE) and the loss of power supply probability (LPSP) over a project lifetime of 25 years to improve the isolated operation of the microgrid. The aim of this study is to investigate an optimum combination of different energy systems which can supply electricity to a rural area in Egypt. The results show the COE for the optimal model was found 0.139 $/kWh which is less than half of the PV or WT system.
Volume: 16
Issue: 2
Page: 221-231
Publish at: 2015-11-01

Range-Free Localization Schemes for Wireless Sensor Networks

10.11591/ijeecs.v16.i2.pp323-332
R. Khadim , M. Erritali , A. Maaden
Localization of nodes is one of the key issues of wireless sensor network (WSN) that gained a wide attention in recent years. The existing localization techniques can be generally categorized into two types: range-based and range-free. Compared with rang-based schemes, the range-free schemes are more cost-effective, because no additional ranging devices are needed. As a result, we focus our research on the range-free schemes. In this paper we study three types of range-free location algorithms to compare the localization error and energy consumption of each one. Centroid algorithm requires a normal node has at least three neighbor anchors, while DV-hop algorithm doesn’t have this requirement. The third studied algorithm is the amorphous algorithm similar to DV-Hop algorithm, and the idea is to calculate the hop distance between two nodes instead of the linear distance between them .The simulation results show that the localization accuracy of the amorphous algorithm is higher than that of other algorithms and the energy consumption does not increase too much.
Volume: 16
Issue: 2
Page: 323-332
Publish at: 2015-11-01

SecureDBaaS Model for Accessing Encrypted Cloud Databases

10.11591/ijeecs.v16.i2.pp333-340
Palle Jagadeeswaraiah , M.R. Pavan Kumar
Cloud computing has recently emerged being a compelling paradigm that pertains to managing and delivering services over the web. The particular prevalent problem connected with cloud is confidentiality, security, as well as reliability etc., in which how the cloud provider assures. To recognize this, a novel architecture is usually introduced that will integrates cloud database services and as well executing concurrent operations on encrypted information. Also a new homomorphic encryption algorithm will likely be incorporated to offer confidentiality as well as concurrent execution of various SQL operations. This will be the first option supporting quite a few distributed clienteles to access encrypted cloud databases. One of main thing is that it eliminates advanced proxies in between cloud user and provider.The performance on the architecture is usually calculated by means of theoretical and practical results which are subjected to TPC-C benchmark standard tools for a number of clients as well as network latencies.
Volume: 16
Issue: 2
Page: 333-340
Publish at: 2015-11-01

Machine Learning Based Automotive Forensic Analysis for Mobile Applications Using Data Mining

10.11591/ijeecs.v16.i2.pp350-354
MD. Hussain Khan , G. Pradeepini
Phone is a device which provides communication between the people through voice, text, video etc. Now a day’s people may leave without food but not without using phones. No of operating systems are working with various versions and various security issues are working. Security is very important task in Mobiles and mobile apps. To improve the security status of mobiles, existing methodology is using cloud computing and data mining. Out traditional method is named as MobSafe to identify the mobile apps antagonism or graciousness. In the proposed system, we adopt Android Security Evaluation Framework (ASEF) and Static Android Analysis Framework (SAAF).In this paper, our proposed system works on machine learning to conduct automotive forensic analysis of mobile apps based on the generated multifaceted data in this stage.
Volume: 16
Issue: 2
Page: 350-354
Publish at: 2015-11-01

Quantitative Analysis of Plant Growth Exposed to Electric Fields

10.11591/ijeecs.v16.i2.pp207-220
Hussein Ahmad , Mohd Hafizi Ahmad , Noor 'Aliaa Awang , Izzah Hazirah Zakaria
Electromagnetic radiations present in the environment has a profound effect on the growth of vegetable plant primarily grown under the high power transmission lines. The high electric field generated due to ultra high voltage causes the increase and reduction in the size of the plants. Numerous research have been carried out to investigate the effect of electric field on the plants. However, the knowledge in term of quantitative analysis on the effect of electric field on the growth of vegetables is not entirely understood. Thus, this paper presents a study conducted to investigate the effect of high voltage DC electric fields on the young vegetables growth namely ‘Choy Sam’ and bean sprout. The experimental setup was designed which composed of two parallel plate electrodes. This research was focused on the percentage of germination and growing rate of young vegetables. The growth of the young vegetables during exposure was calculated by using statistical methods. The analysis of the results showed that the electric fields and the electric fields treated water have influenced the germination rate and height of stems of both young vegetables causing the increase in stem height. 
Volume: 16
Issue: 2
Page: 207-220
Publish at: 2015-11-01

Design and Implementation of Recursive Least Square Adaptive Filter Using Block DCD approach

10.11591/ijres.v4.i3.pp209-212
Sachin S. Khanande , S.J. Honade
Due to the explosive growth of multimedia application and tremendous demands in Very Large Scale Integrated (VLSI), there is a need of high speed and low power digital filters for digital signal processing applications. In Digital Signal Processing (DSP) systems, Finite Impulse Response (FIR) filters are one of the most common components which is used, by convolving the input data samples with the desired unit sample response of the filter. The proposed work deals with the design and implementation of RLS adaptive filter using block DCD approach. The evaluation of speed, area and power for proposed work will be done. Also, the comparison of the proposed design with the existing will be carried out for various input combinations.
Volume: 4
Issue: 3
Page: 209-212
Publish at: 2015-11-01

Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS

10.11591/ijres.v4.i3.pp178-184
Ajeesh Kumar , N. Saraswathi
This paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concern
Volume: 4
Issue: 3
Page: 178-184
Publish at: 2015-11-01

Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach

10.11591/ijres.v4.i3.pp213-218
Vandana Shukla , O. P. Singh , G. R. Mishra , R. K. Tiwari
Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.
Volume: 4
Issue: 3
Page: 213-218
Publish at: 2015-11-01

Radar Target Characteristics Extraction using Polarization Scattering Matrix

10.11591/ijeecs.v16.i2.pp308-315
L Vijaya Lakshmi , A Jaya Lakshmi , M N V S S Kumar , P Sirish Kumar
Now a day’s characterization of targets using radar is very important in Air Traffic Control, Defense, and Stealth etc.  In order to know the characteristics of the target it is very essential to know the polarization properties of that particular target which depends upon scattering nature of the target.  The polarization properties are important for radar target besides amplitude, phase and frequency. The polarization may be potentially used to improve target detection, anti-interference, and radar target recognition. Polarization properties of a target can be obtained using polarization scattering matrix (PSM). In this paper the polarization matrix of various geometrical shapes are derived.  For radar target recognition (RTR), a method using properties of the polarization scattering matrix (PPSM) is presented in this paper. A dipole has been considered to calculate the polarization matrix and polarization properties. The properties of the polarization scattering matrix: the determinant, Trace of Power Scattering Matrix, Depolation, Eigen polarization angle and Module of Polarization Ellipticity are analyzed. These properties are analyzed for different orientation angles of the targets.
Volume: 16
Issue: 2
Page: 308-315
Publish at: 2015-11-01

NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms

10.11591/ijres.v4.i3.pp185-191
Chakrapani Kannan
Cryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor.  NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits.
Volume: 4
Issue: 3
Page: 185-191
Publish at: 2015-11-01

An Efficient approach for Design and Testing of FPGA Programming using LabVIEW

10.11591/ijres.v4.i3.pp192-200
Naresh Kumar Reddy , N. Suresh
Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.
Volume: 4
Issue: 3
Page: 192-200
Publish at: 2015-11-01

Development of BSP for ARM9 Evaluation Board

10.11591/ijres.v4.i3.pp161-172
Vinayak Pandit K. , Sanket Dessai , Shilpa Chaudhari
With an increasing usage of ARM9 core for different kinds of applications ranging from data acquisition to Mobile application, there arises the need for developing ARM9 based board. To bring up this board, board supporting package (BSP) is must. Board supporting package virtualizes the platform hardware so that the different drivers can be ported easily on any hardware. The boot loader is the initial stage of firmware, which initializes the hardware components presents on the board. A universal Bootloader is chosen and is to be customized with respect to target board. In the later section bootloader is interfaced to the kernel which is obtained form an authorized distributor under general purpose license. The customized board specific routines as well drivers are ported onto the hardware. Then the compiled kernel image is ported onto the target board using a debugger and SAM-BA utility. Linux kernel has seen major releases; the basic architecture of the Linux kernel has remained more or less unchanged. The latest 2.6 version of Linux kernel is ported onto target hardware. Kernel support for many architectures and high-end I/O devices gives the independence to choose appropriate hardware for developing system. The bootloader customization is the critical step, which involves a lot of modifications in the header files. BSP components such as bootloader, kernel is compiled using GNU tool chain; obtained image is ported on target using debugger. BSP porting is a very complex task, which required knowledge of hardware and software control sequence and boot strategy of the controller.
Volume: 4
Issue: 3
Page: 161-172
Publish at: 2015-11-01

Dynamic Partial Reconfiguration with FIR Filter Application

10.11591/ijres.v4.i3.pp201-208
Noopur Astik
Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of Field Programmable Gate Array (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented
Volume: 4
Issue: 3
Page: 201-208
Publish at: 2015-11-01
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