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27,404 Article Results

An approach for Assessing Harmonic Emission Level Based on Robust Partial Least Squares Regression

10.11591/ijeecs.v12.i7.pp4981-4987
Xiang Li , Minyou Chen , Yongwei Zheng , Shan Cheng , Feng Li
An approach to evaluate harmonic contributions at the point of common coupling is presented in this paper. The proposed approach is based on robust partial least squares regression, which estimates system harmonic impedance by utilizing the signals of harmonic voltage and current measured synchronously at the point of common coupling. Consequently according to the IEC Technical Report 61000-3-6 the harmonic emission level of user is calculated. The presented method overcomes the disadvantage of variable dependence in establishing of the system model and reduces or removes the effect of outlying data points. The method is verified through a simulation study and with extensive field measurements.
Volume: 12
Issue: 7
Page: 4981-4987
Publish at: 2014-07-01

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System

10.11591/ijres.v3.i2.pp76-84
Manoj Kumar A , R V Nadagouda , R Jegan
Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.
Volume: 3
Issue: 2
Page: 76-84
Publish at: 2014-07-01

Framework of Software Testing Based on Cloud Computing

10.11591/ijeecs.v12.i7.pp5678-5684
Yang Bensehng , Yuan Xiangmeng , Huang Xiaoguang
For the problem that efficiency is low and cost is high existing in the traditional software testing method, the paper tested software using cloud testing technology. It introduced related technologies including cloud testing, and described the design of overall architecture of the system in details, designed and implemented the scheduling module using a high priority first scheduling based on dynamic priority. The results of the Matlab simulation experiment show that this scheduling algorithm can reduce test cost and realize the automation of software testing under the condition of significantly improving test efficiency and resource utilization.
Volume: 12
Issue: 7
Page: 5678-5684
Publish at: 2014-07-01

Simplifications of the Rule base for the stabilization of Inverted Pendulum System

10.11591/ijeecs.v12.i7.pp5225-5234
Tharwat O. S. Hanafy , Mohamed K Metwally
Control of an inverted pendulum on a carriage which moves in a horizontal path, is one of the classic problems in the area of control. The basic aim of our work was to design appropriate controller to control the angle of the pendulum and the position of the cart in order to stabilize the inverted pendulum system. The main objective of this paper to keep the stabilization of the inverted pendulum based on the simplification of rule base. The proposed fuzzy control scheme successfully fulfills the control objectives and also has an excellent stabilizing ability to overcome the external impact acting on the pendulum system. The effectiveness of this controller is verified by experiments on a simple inverted pendulum with fixed cart length.
Volume: 12
Issue: 7
Page: 5225-5234
Publish at: 2014-07-01

FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique

10.11591/ijres.v3.i2.pp39-48
Pradeep C , Radhakrishnan R
This paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed  to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations  many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm.  For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility.
Volume: 3
Issue: 2
Page: 39-48
Publish at: 2014-07-01

Direct Virtual Power Control

10.11591/ijeecs.v12.i7.pp5144-5153
Li Xiang , Han Minxiao
A direct virtual power control algorithm is presented in this paper for VSC-HVDC startup. This control algorithm is based on direct power control (DPC) and expands the range of DPC. When the VSC converter AC side open circuit or the AC side current is zero, the control algorithm maintains the DPC feedback loop by introducing a virtual power, so that the DPC is able to control the AC output voltage amplitude and frequency stability before the VSC converter connecting to the grid network and keep consistent with the grid connection point. This algorithm process is simple, containing most of the DPC control module, and consistent with the DPC structure. Therefore, the control algorithm switches smoothly before and after the VSC converter connecting to the grid. This paper uses PSCAD / EMTDC software platform and laboratory hardware circuit experiments to test and verify the correctness and validity of the control algorithm.
Volume: 12
Issue: 7
Page: 5144-5153
Publish at: 2014-07-01

Design of AES Algorithm for 128/192/256 Key Length in FPGA

10.11591/ijres.v3.i2.pp49-53
Pravin V. Kinge , S.J. Honale , C.M. Bobade
The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).
Volume: 3
Issue: 2
Page: 49-53
Publish at: 2014-07-01

A New Digital Image Hiding Algorithm Based on Wavelet Packet Transform and Singular Value Decomposition

10.11591/ijeecs.v12.i7.pp5408-5413
Yueli Cui , Shiqing Zhang , Zhigang Chen , Wei Zheng
The paper presents a new digital image hiding algorithm based on wavelet packets transform and singular value decomposition. The low-frequency sub-band of wavelet packets transform has strong anti-jamming capacity and the singular value has very strong stability. The presented algorithm implements bit plane decomposition on the secret image and wavelet packet decomposition on the carrier image. Then, it hides the bit planes with important information into the singular value matrix of the low frequency coefficient matrix, and also hides the bit planes with secondary information into the remainder sub-band matrix with higher entropy energy. The hiding location is adaptively determined by the carrier image. The experimental results indicate that, the proposed image hiding algorithm has strong robustness and anti-attack, and it also has good invisibility and big capability.
Volume: 12
Issue: 7
Page: 5408-5413
Publish at: 2014-07-01

Design and Implementation of Adaptive FIR filter using Systolic Architecture

10.11591/ijres.v3.i2.pp54-61
Ravi H Bailmare , S.J. Honale , Pravin V Kinge
The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.
Volume: 3
Issue: 2
Page: 54-61
Publish at: 2014-07-01

Construction Protocol of Wireless Sensor Network based on Centralized Clustering Routing and Time Division Multiplexing MAC Protocol

10.11591/ijeecs.v12.i7.pp5591-5598
Shitao Yan , Mianrong Yang
LEACH is a routing protocol based on clustering in wireless sensor networks and is based on a low power adaptive hierarchical routing algorithm design of wireless sensor network. Time division multiplexing mechanism is for each wireless sensor network node distribution independent time slots for data transceiver, and the node into sleep state in other free time slot. This paper introduces MAC protocol based on time division multiplexing. The paper proposes construction protocol of wireless sensor network based on centralized clustering routing and time division multiplexing MAC protocol. The simulation results show that the LEACHEE protocol can effectively reduce network energy consumption, prolong the network life cycle.
Volume: 12
Issue: 7
Page: 5591-5598
Publish at: 2014-07-01

A Design of Rapid Pulsed Intelligent Charging Circuit

10.11591/ijeecs.v12.i7.pp4996-5002
Zhang Lefang , Li Xiaohong , Ren Zhihong
As known that the traditional DC constant voltage charging equipment not only can cause the battery overcharge or insufficient charging, but also the charging time is too long. In the paper, based on the theory of pulse charging method and the design of the pulsed fast intelligent charging equipment is presented, the implementation of hardware and software process of the system is given out, the analysis of the results show that it can effectively prevent overcharge and low charge phenomenon in the charging process of battery.
Volume: 12
Issue: 7
Page: 4996-5002
Publish at: 2014-07-01

Communication and Calibraton of Sensing Meters

10.11591/ijeecs.v12.i7.pp4905-4914
Harrouz Abdelkader , Omar Harrouz , Ali Benatiallah
The purpose of this paper is to review the essential definitions, roles and characteristics of communication on metering system. We discuss measurement, data acquisition and metrological control of a signal sensor from dynamic metering system. After that, we present instruments of sensor communication with more detailed discussions to the reference standards and the important fundamental parameters to consider when designing a dynamic communication metering system. We finished with control and calibration of turbine flow meter and we given resultats expermentaly of this work.
Volume: 12
Issue: 7
Page: 4905-4914
Publish at: 2014-07-01

Improved Compressed Sensing Matrixes for Insulator Leakage Current Data Compressing

https://ijeecs.iaescore.com/index.php/IJEECS/article/view/3500
Zhai Xueming , You Xiaobo , Dewen Wang
Insulator fault may lead to the accident of power network，thus the on-line monitoring of insulator is very significant. Low rates wireless network is used for data transmission of leakage current. Determination of the measurement matrix is the significant step for realizing the compressed sensing theory. This article comes up with new sparse matrices which can be used as compressed sensing matrices to make data compression and reconstruction of leakage current with the compressed sensing. This theory can achieve pretty good results. And then this article performs that the reconstitution effect is almost the same using the measurement matrix of Toeplitz matrix, circulant matrix or sparse matrix, as using a classical measurement matrix. DOI : http://dx.doi.org/10.11591/telkomnika.v12i6.1419
Volume: 12
Issue: 6
Page: 4258-4263
Publish at: 2014-06-01

Motion Compensation Technique Based On Fractional Fourier Transform

https://ijeecs.iaescore.com/index.php/IJEECS/article/view/3522
Tan Gewei , Pan Guangwu , Lin Eei
Fractional Fourier transform(FrFT) is a kind of generalized Fourier transform, which processes signals in the unified time-frequency domain and the linear frequency modulation signal can be well focused after FrFT. Motion error is an important factor affecting the SAR resolution, pointing to the problem that the effect of error elimination is not obvious in processing non-stationary motion error using the traditional FFT based motion compensation combined SAR imaging algorithm, FrFT based two-step motion compensation combined wavenumber domain algorithm and sub-aperture wide beam motion compensation algorithm are put forward in this paper, which are expected to eliminate the influence of motion error more effectively, so as to obtain high quality SAR images. The simulation results and the imaging results of real SAR data show that the proposed algorithms indeed eliminate the influence of motion error effectively. (the real SAR data provided by Institute of Electronics, Chinese Academy of Sciences). DOI : http://dx.doi.org/10.11591/telkomnika.v12i6.5478
Volume: 12
Issue: 6
Page: 4427-4437
Publish at: 2014-06-01

Application of Grey Correlation Degree and TOPSIS Method in Evaluation of Power Quality

https://ijeecs.iaescore.com/index.php/IJEECS/article/view/3489
Fan Li-Guo , Wang Hai-Feng
Aiming at solving multi-criteria decision problems in power quality, a new decision-making method based on grey correlation degree and TOPSIS is proposed. On the basis of introducing the concept of grey correlation degree into traditional TOPSIS, a new relative similarity degree is established to decide power quality by combining Euclidean distance with grey correlation degree. Error originated from biased thinking due to subjective and objective factors in decision-making problem when using single method could be overcome by using the method and reliability of evaluation result in electric material tendering can be boosted up. Example shows that power quality could be effectively estimated by use the method and the method is an effective instruction for PQ evaluation. DOI : http://dx.doi.org/10.11591/telkomnika.v12i6.5251
Volume: 12
Issue: 6
Page: 4142-4147
Publish at: 2014-06-01
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