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28,593 Article Results

Study of Additive Dither on Restraining Signal Truncation Error

10.11591/ijeecs.v12.i7.pp5420-5429
Tao Liu , Shulin Tian , Zhigang Wang , Lianping Guo
Owing to the limited calculation precision during digital signal processing, the intermediate stages’ signal-bit-width truncation should be executed to realize the conversion from high precision to low one. As method of direct truncation will degenerate the Spurious Free Dynamic Range (SFDR) performance of the output signal, this paper proposed that additional digital dither should be added before operation of truncation, which could decline the harmonic distortion efficiently and extend the dynamic range of the truncated signal significantly. Two simulations for truncation operation towards signal with additive Gaussian dither and uniform dither are carried out to prove the validity of the proposed method. Comparative studies demonstrate that the proposed algorithm applied in Gaussian dithering and uniform dithering could improve the output SFDR performance by about 16dB and 15dB respectively.
Volume: 12
Issue: 7
Page: 5420-5429
Publish at: 2014-07-01

Algorithm of Multi Sensor Data Fusion based on BP Neural Network and Multi-scale Model Predictive Control

10.11591/ijeecs.v12.i7.pp5316-5323
Guo Wang , Dong Dai
Multi sensor data fusion is the data from multiple sensors and information from the relevant database are combined, which obtained judgment and description that can not achieve the goal, more accurate and complete by any single sensor. BP neural network is a kind of artificial neural network based on error back-propagation algorithm. It adopts adding hidden layer, to estimate the error directly leading layer of output layer by the error output. The paper presents Algorithm of multi sensor data fusion based on BP neural network and multi-scale model predictive control. The multi-scale model predictive control can not only obtain the previous information, and increase the flexibility in modeling and optimal phase.
Volume: 12
Issue: 7
Page: 5316-5323
Publish at: 2014-07-01

Key Technology on Middleware-based Dynamic Traffic Information Platform

10.11591/ijeecs.v12.i7.pp5661-5568
Lei Wu , Tai Yang , Licai Yang
According to traffic information of multi-source heterogeneity and complexity of information processing, the architecture of the dynamic traffic information platform based on middleware is proposed, which enhanced the system stability, generality, and efficiency depending on the high integration and scalability of middleware. This middleware-based platform unifies and encodes the data from all sorts of detectors, and integrates the multi-mode transmission, data preprocessing, and data fusion. On the publishing stage, this platform realizes the interactions between different publishing devices and traffic database through an independent traffic information publishing middleware. The proposed platform overcomes the data loss and data noise, decreases the data redundancy due to the heterogeneous multi-source data, and ensures the data accuracy with better security and expandability. The performance is efficient, reliable with cross-platform information transmission.
Volume: 12
Issue: 7
Page: 5661-5568
Publish at: 2014-07-01

Design and Development of ARM9 Evaluation Kit for Embedded Applications

10.11591/ijres.v3.i2.pp62-75
Nikhil Alex Thomas , Sanket Dessai , S.G. ShivaPrasad Yadav , Shilpa Chaudhari
In contrast with low end microprocessor, ARM9 core is quite a sophisticated processor. The Evaluation kit plays an important role in the prototype development and verification of the system design before taking to its actual system development hence it’s provide better confidence to the designer. In this paper a project for the Evaluation kit has been designed for embedded system engineer to implement and confirm the functionality of their operating systems which could lead to a comfortable deployment. The independent modules for the interfaces of the ARM9 processor have been designed and the schematics have been developed using OrCAD. From the tested schematics designed in OrCAD, the related PCB is designed using CADSTAR. An eight-layer board is designed for its signal integrity and complexity of the schematic designed. The designed PCB layer is then calibrated and Gerber files are then made and passed on the PCB board manufacturer for PCB fabrication. The PCB board made is then tested for interconnection continuity using multi-meter as the components are loaded on to the board.
Volume: 3
Issue: 2
Page: 62-75
Publish at: 2014-07-01

An approach for Assessing Harmonic Emission Level Based on Robust Partial Least Squares Regression

10.11591/ijeecs.v12.i7.pp4981-4987
Xiang Li , Minyou Chen , Yongwei Zheng , Shan Cheng , Feng Li
An approach to evaluate harmonic contributions at the point of common coupling is presented in this paper. The proposed approach is based on robust partial least squares regression, which estimates system harmonic impedance by utilizing the signals of harmonic voltage and current measured synchronously at the point of common coupling. Consequently according to the IEC Technical Report 61000-3-6 the harmonic emission level of user is calculated. The presented method overcomes the disadvantage of variable dependence in establishing of the system model and reduces or removes the effect of outlying data points. The method is verified through a simulation study and with extensive field measurements.
Volume: 12
Issue: 7
Page: 4981-4987
Publish at: 2014-07-01

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System

10.11591/ijres.v3.i2.pp76-84
Manoj Kumar A , R V Nadagouda , R Jegan
Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.
Volume: 3
Issue: 2
Page: 76-84
Publish at: 2014-07-01

Framework of Software Testing Based on Cloud Computing

10.11591/ijeecs.v12.i7.pp5678-5684
Yang Bensehng , Yuan Xiangmeng , Huang Xiaoguang
For the problem that efficiency is low and cost is high existing in the traditional software testing method, the paper tested software using cloud testing technology. It introduced related technologies including cloud testing, and described the design of overall architecture of the system in details, designed and implemented the scheduling module using a high priority first scheduling based on dynamic priority. The results of the Matlab simulation experiment show that this scheduling algorithm can reduce test cost and realize the automation of software testing under the condition of significantly improving test efficiency and resource utilization.
Volume: 12
Issue: 7
Page: 5678-5684
Publish at: 2014-07-01

Simplifications of the Rule base for the stabilization of Inverted Pendulum System

10.11591/ijeecs.v12.i7.pp5225-5234
Tharwat O. S. Hanafy , Mohamed K Metwally
Control of an inverted pendulum on a carriage which moves in a horizontal path, is one of the classic problems in the area of control. The basic aim of our work was to design appropriate controller to control the angle of the pendulum and the position of the cart in order to stabilize the inverted pendulum system. The main objective of this paper to keep the stabilization of the inverted pendulum based on the simplification of rule base. The proposed fuzzy control scheme successfully fulfills the control objectives and also has an excellent stabilizing ability to overcome the external impact acting on the pendulum system. The effectiveness of this controller is verified by experiments on a simple inverted pendulum with fixed cart length.
Volume: 12
Issue: 7
Page: 5225-5234
Publish at: 2014-07-01

FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique

10.11591/ijres.v3.i2.pp39-48
Pradeep C , Radhakrishnan R
This paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed  to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations  many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm.  For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility.
Volume: 3
Issue: 2
Page: 39-48
Publish at: 2014-07-01

Direct Virtual Power Control

10.11591/ijeecs.v12.i7.pp5144-5153
Li Xiang , Han Minxiao
A direct virtual power control algorithm is presented in this paper for VSC-HVDC startup. This control algorithm is based on direct power control (DPC) and expands the range of DPC. When the VSC converter AC side open circuit or the AC side current is zero, the control algorithm maintains the DPC feedback loop by introducing a virtual power, so that the DPC is able to control the AC output voltage amplitude and frequency stability before the VSC converter connecting to the grid network and keep consistent with the grid connection point. This algorithm process is simple, containing most of the DPC control module, and consistent with the DPC structure. Therefore, the control algorithm switches smoothly before and after the VSC converter connecting to the grid. This paper uses PSCAD / EMTDC software platform and laboratory hardware circuit experiments to test and verify the correctness and validity of the control algorithm.
Volume: 12
Issue: 7
Page: 5144-5153
Publish at: 2014-07-01

Design of AES Algorithm for 128/192/256 Key Length in FPGA

10.11591/ijres.v3.i2.pp49-53
Pravin V. Kinge , S.J. Honale , C.M. Bobade
The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).
Volume: 3
Issue: 2
Page: 49-53
Publish at: 2014-07-01

A New Digital Image Hiding Algorithm Based on Wavelet Packet Transform and Singular Value Decomposition

10.11591/ijeecs.v12.i7.pp5408-5413
Yueli Cui , Shiqing Zhang , Zhigang Chen , Wei Zheng
The paper presents a new digital image hiding algorithm based on wavelet packets transform and singular value decomposition. The low-frequency sub-band of wavelet packets transform has strong anti-jamming capacity and the singular value has very strong stability. The presented algorithm implements bit plane decomposition on the secret image and wavelet packet decomposition on the carrier image. Then, it hides the bit planes with important information into the singular value matrix of the low frequency coefficient matrix, and also hides the bit planes with secondary information into the remainder sub-band matrix with higher entropy energy. The hiding location is adaptively determined by the carrier image. The experimental results indicate that, the proposed image hiding algorithm has strong robustness and anti-attack, and it also has good invisibility and big capability.
Volume: 12
Issue: 7
Page: 5408-5413
Publish at: 2014-07-01

Design and Implementation of Adaptive FIR filter using Systolic Architecture

10.11591/ijres.v3.i2.pp54-61
Ravi H Bailmare , S.J. Honale , Pravin V Kinge
The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.
Volume: 3
Issue: 2
Page: 54-61
Publish at: 2014-07-01

Construction Protocol of Wireless Sensor Network based on Centralized Clustering Routing and Time Division Multiplexing MAC Protocol

10.11591/ijeecs.v12.i7.pp5591-5598
Shitao Yan , Mianrong Yang
LEACH is a routing protocol based on clustering in wireless sensor networks and is based on a low power adaptive hierarchical routing algorithm design of wireless sensor network. Time division multiplexing mechanism is for each wireless sensor network node distribution independent time slots for data transceiver, and the node into sleep state in other free time slot. This paper introduces MAC protocol based on time division multiplexing. The paper proposes construction protocol of wireless sensor network based on centralized clustering routing and time division multiplexing MAC protocol. The simulation results show that the LEACHEE protocol can effectively reduce network energy consumption, prolong the network life cycle.
Volume: 12
Issue: 7
Page: 5591-5598
Publish at: 2014-07-01

A Design of Rapid Pulsed Intelligent Charging Circuit

10.11591/ijeecs.v12.i7.pp4996-5002
Zhang Lefang , Li Xiaohong , Ren Zhihong
As known that the traditional DC constant voltage charging equipment not only can cause the battery overcharge or insufficient charging, but also the charging time is too long. In the paper, based on the theory of pulse charging method and the design of the pulsed fast intelligent charging equipment is presented, the implementation of hardware and software process of the system is given out, the analysis of the results show that it can effectively prevent overcharge and low charge phenomenon in the charging process of battery.
Volume: 12
Issue: 7
Page: 4996-5002
Publish at: 2014-07-01
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