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Implementation of tourism circuit concept in an android-based tourist navigation application through A* algorithm

10.11591/ijeecs.v24.i2.pp986-992
Jonardo R. Asor , Gene Marck B. Catedrilla , Cris Q. De Leon , Sharon L. Ramos
Circuit tourism allows for inclusive growth of tourism since it allows for multi-site visits. Normally three or more tourist attractions are linked together in a tour of the tourist’s choosing. The main objective of this study is to develop an android-based application for searching tourist spots in Los Baños, Laguna, Philippines that is also capable of recommending succeeding places to visit using A* algorithm. Upon development of the application, this paper proves that A* algorithm can be used to recommend another tourist spot by analyzing the distance of the tourist spots near the user, and the most convenient routes through which they can be reached. Based on backward and forward compatibility testing, the application is operating system friendly, since it can be used in lower versions of android. Further, it is shown in the users’ evaluation that the application is acceptable to the locals of Los Baños, Laguna, Philippines. The application also contributes to advertising other tourist spots in the said municipality, specially those who were not so popular to the tourists.
Volume: 24
Issue: 2
Page: 986-992
Publish at: 2021-11-01

ACCESS - IoT enabled smart lock

10.11591/ijres.v10.i3.pp176-185
Harshith Gadupu , Osa Mokharji , Raunak Kankaria , Shrey Kumar , Kayalvizhi Jayavel
ACCESS is a centrally controlled extensible security system - a system for enhancing accessibility and security methods. Security is an important matter of concern and everyone wants things easy and fast with the advancement of technology. Many IoT engineers are inclined towards home automation today. An area of recent interest is the automation of lock and key systems of homes and workplaces. This paper comprises mechanisms to view visitors of households, machinery, or any appliance that may be remotely controlled through a mobile application. Owners or supervisors can keep a watch on the guests and choose whom they want to grant entry to. This is conducted by providing the guests with temporary access permission for a validity period of the owner’s choice. They can also simultaneously monitor the activities of the guests.
Volume: 10
Issue: 3
Page: 176-185
Publish at: 2021-11-01

A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

10.11591/ijres.v10.i3.pp221-229
Mohd Tafir Mustaffa
Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.
Volume: 10
Issue: 3
Page: 221-229
Publish at: 2021-11-01

Heuristic algorithms for dynamic scheduling of moldable tasks in multicore embedded systems

10.11591/ijres.v10.i3.pp157-167
Takuma Hikida , Hiroki Nishikawa , Hiroyuki Tomiyama
Dynamic scheduling of parallel tasks is one of the efficient techniques to achieve high performance in multicore systems. Most existing algorithms for dynamic task scheduling assume that a task runs on one of the multiple cores or a fixed number of cores. Existing researches on dynamic task scheduling methods have evaluated their methods in different experimental environments and models. In this paper, the dynamic task scheduling methods are systematically rearranged and evaluated.
Volume: 10
Issue: 3
Page: 157-167
Publish at: 2021-11-01

Exploiting outage performance in device-to-device for user grouping

10.11591/ijeecs.v24.i2.pp904-909
Dinh-Thuan Do , Chi-Bao Le
The spectrum efficiency and massive connections are joint designed in new form of device-to-device for user grouping. A pair of users is implemented with nonorthogonal multiple access (NOMA) systems. Although NOMA benefits to such system in term of the serving users, device to device (D2D) faces the interference from normal cellular users (CUE). In particular, we derive exact formulas of outage probability to show system performance. In this article, we compare two schemes to find relevant scheme to implement in practice. The frame structure is designed with two timeslot related to uplink and downlink between the base station and D2D users. We confirm the better scheme in numerical result by considering the impacts of many parameters on outage performance.
Volume: 24
Issue: 2
Page: 904-909
Publish at: 2021-11-01

Digital brain: Model-based framework for dependable electroencephalogram sensing and actuation in internet of things system

10.11591/ijres.v10.i3.pp168-175
R. J. Kavitha , Saravanan K. K.
Real-time brain internet of thing (IoT) frameworks are expensive. But, creating a cheaper framework has been quickened incredibly by the superior investigation that's being done on virtual brain. The passing of an imperative individual on a mystery mission is considered delicate data and must be taken care of with as much security as conceivable. By guaranteeing this discreteness, the time taken for the message of their passing to reach the pertinent specialist is expanded to up to a few days. The time taken to provide the message is as well. These days, the advancements in equipment expanding the capacities of the virtual brain and of the wearable brain IoT sensors have made the advancement of various unused program systems conceivable for engineers to make valuable applications that combine the human brain with IoT. Different tactile pathways are too empowered for communications of the human brain with bigger measured data. The fundamental point of this extend is to transfer secret records onto the clouds safely.
Volume: 10
Issue: 3
Page: 168-175
Publish at: 2021-11-01

Intruder detection and recognition using different image processing techniques for a proactive surveillance

10.11591/ijeecs.v24.i2.pp843-852
Nelson C. Rodelas , Melvin A. Ballera
To innovate a proactive surveillance camera, there is a need for efficient face detection and recognition algorithm. The researchers used one of the ViolaJones algorithm and used different image processing techniques to recognize intruders or not. The goal of the research is to recognize the fastest way on how the homeowners will be informed if an intruder or burglar enters their home using a proactive surveillance device. This device was programmed based on the different recognition algorithms and a criteria evaluation framework that could recognize intruders and burglars and the design used was developmental research to satisfy the research problem. The researchers used the Viola-Jones algorithm for face detection and five algorithms for face recognition. The criteria evaluation was used to identify the best face recognition algorithm and was tested in a real-world situation and captured a series of images camera and processed by proactive face detection and recognition. The result shows that the system can detect and recognize intruders and proactively send a notification to the homeowners via mobile application. It is concluded that the system can recognize the intruders and proactively notify the household members using the mobile applications and activate the alarm system of the house.
Volume: 24
Issue: 2
Page: 843-852
Publish at: 2021-11-01

FPGA based co-design of a speed fuzzy logic controller applied to an autonomous car

10.11591/ijres.v10.i3.pp195-211
Emna Aridhi , Decebal Popescu , Abdelkader Mami
This paper invests in FPGA technology to control the speed of an autonomous car using fuzzy logic. For that purpose, we propose a co-design based on a novel fuzzy controller IP. It was developed using the hardware language VHDL and driven by the Zynq processor through an SDK software design written in C. The proposed IP acts according to the ambient temperature and the presence or absence of an obstacle and its distance from the car. The partitioning of the co-design tasks divides them into hardware and software parts. The simulation results of the fuzzy IP and those of the complete co-design implementation on a Xilinx Zynq board showed the effectiveness of the proposed controller to meet the target constraints and generate suitable PWM signals. The proposed hardware architecture based on 6-LUT blocks uses 11 times fewer logic resources than other previous similar designs. Also, it can be easily updated when new constraints on the system are to be considered, which makes it suitable for many related applications. Fuzzy computing was accelerated thanks to the use of digital signal processing blocks that ensure parallel processing. Indeed, a complete execution cycle takes only 7 us.
Volume: 10
Issue: 3
Page: 195-211
Publish at: 2021-11-01

Modified limited-memory Broyden-Fletcher-Goldfarb-Shanno algorithm for unconstrained optimization problem

10.11591/ijeecs.v24.i2.pp1027-1035
Muna M. M. Ali
The use of the self-scaling Broyden-Fletcher-Goldfarb-Shanno (BFGS) method is very efficient for the resolution of large-scale optimization problems, in this paper, we present a new algorithm and modified the self-scaling BFGS algorithm. Also, based on noticeable non-monotone line search properties, we discovered and employed a new non-monotone idea. Thereafter first, an updated formula is exhorted to the convergent Hessian matrix and we have achieved the secant condition, second, we established the global convergence properties of the algorithm under some mild conditions and the objective function is not convexity hypothesis. A promising behavior is achieved and the numerical results are also reported of the new algorithm.
Volume: 24
Issue: 2
Page: 1027-1035
Publish at: 2021-11-01

SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

10.11591/ijres.v10.i3.pp237-248
Matias Javier Oliva , Pablo Andrés García , Enrique Mario Spinelli , Alejandro Luis Veiga
Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
Volume: 10
Issue: 3
Page: 237-248
Publish at: 2021-11-01

Neural net implementation of steam properties on FPGA

10.11591/ijres.v10.i3.pp186-194
R. V. S. Krishna Dutt , R. Ganesh , P. Premchand
Real time applications like model predictive control, monitoring and data reconciliation of power plants and industrial processes employ nonlinear mathematical models and require thermodynamic properties and their derivatives of working fluids. Applications like super heater temperature control based on energy balance and real time data reconciliation, require an efficient and a compact method for simultaneous estimation of thermodynamic properties, and their partial derivatives suitable for implementation in field-programmable gate array (FPGA). However, the complex mathematical formulations of these properties prohibit direct implementations in FPGAs. Single artificial neural network (ANN) architecture is used to replace the entire code in higher level languages, running into a few thousand lines. FPGA implementation of a compact neural network for the entire range of thermodynamic properties is presented. Large arguments in sigmoid function are factored into a product of integer and a fractional part which is represented using series approximation with five terms only and the integers are represented in look up table (LUT). This ensures optimum storage and computational burden for the above applications. The ANN is implemented in IEEE 754 floating point with synthesis in Xilinx ISE design suite using Verilog HDL. The results are presented for a typical pressure versus saturation temperature.
Volume: 10
Issue: 3
Page: 186-194
Publish at: 2021-11-01

Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation

10.11591/ijres.v10.i3.pp212-220
Chiranjeevi G. N. , Subhash Kulkarni
The bulks of image processing algorithms are either two-dimensional (2D) or confined by their very nature. As a result, the 2D convolution function has a large impact on picture processing requirements. The methodology of 2D convolution and media access control (MAC) design can also be used to perform a variety of image processing tasks, and even as picture blurring, softening, and feature extraction. The main goal of this research is to develop a more efficient MAC control block-based 2D convolution architecture. This 2D algorithm can be implemented in hardware using fewer modules, multipliers, adders, and control blocks, resulting in significant hardware savings and look up table (LUT) reductions. The simulations were run in Verilog, and the Xilinx Vertex family field programmable gate array (FPGA) was used to build and test them. The recommended 2D convolution architectural solution is significantly faster and consumes significantly less hardware resources than the traditional 2D convolution implementation. The proposed architecture will result in technology that saves a substantial amount of processing time when it comes to LUTs.
Volume: 10
Issue: 3
Page: 212-220
Publish at: 2021-11-01

Design and analysis of linear switched reluctance motor

10.11591/ijeecs.v24.i2.pp704-714
M. Asyraff Md. Aris , R. N. Firdaus , F. Azhar , N. A. Mohd Nasir , M. Z. Aishah
This paper proposes a linear switched reluctance motor (LSRM) to replace the conventional serving that is used in food and beverage (F&B) applications such as a pack of sushi and carbonated drinks. This conventional method is no longer practical as it requires a lot of space which will affect costing and productivity. It’s also has another disadvantage, in which it needs frequent maintenance of the rotational motor, gear, and limit switches. Therefore, this research is about the design and analysis of linear switched reluctance motor (LSRM) for F&B applications. The main objective is to design a LSRM and the finite element method (FEM) is used to simulate the result. The result showed that the 24s/16p was the best model for linear switched reluctance motor (LSRM) design. The model had average force (F_avg) of 28.36 N for input current (I) of 1A. To conclude, this paperprovides a guideline in designing the LSRM for F&B application.
Volume: 24
Issue: 2
Page: 704-714
Publish at: 2021-11-01

Automating the mixing and spraying stage of the instant mashed potato process

10.11591/ijeecs.v24.i2.pp771-779
Guillermo Morales-Romero , Adrián Quispe-Andía , Nicéforo Trinidad-Loli , Beatriz Caycho-Salas , Teresa Guía-Altamirano , Carlos Palacios-Huaraca , Omar Chamorro-Atalaya
The article describes a control logic used to automate the mixing stage of the instant mashed potato process, in order to improve the quality of the final product. Thus, initially the characteristics of the automated process are detailed, specifying the programming logic on the programmable logic controller, to later demonstrate through a data collection process the percentage of improvement in the quality of the final product from the perspective of the users. Indicators: percentage of humidity in the mixing stage, water absorption index (IAA), water solubility index (ISA) and hydrogen potential (pH). The development of the research concludes that the automation of the process, achieved that the IAA index and the ISA index, obtained in the spraying stage, improve by 8.13% and 23.05%, respectively, finding analyzed values within the optimal ranges. This in turn reflected a 39.61% improvement with respect to the humidity percentage, measured in the mixing stage, thus improving the quality of the final product, which brings with it a significant increase of 84.44% in production levels.
Volume: 24
Issue: 2
Page: 771-779
Publish at: 2021-11-01

Image processing using a reconfigurable platform: Pre-processing block hardware architecture

10.11591/ijres.v10.i3.pp230-236
Chiranjeevi G. N. , Subhash Kulkarni
Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic reequipments viz duplicating, zero padding. For KxK kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software-based processing for KxK spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block.
Volume: 10
Issue: 3
Page: 230-236
Publish at: 2021-11-01
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