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29,758 Article Results

Design and implement of high gain and low noise neural amplifier using compensation techniques

10.11591/ijres.v8.i2.pp124-129
N. Manikandan , S. Muruganand , K. Karuppasamy
Electroencephalography is refer to record the electrical signal with respect to brain activity and its reliable EEG information, using this to diagnosis disorder and tumors. However the signal is very difficult to capture and processing due to so many parameter. Mainly this signal is very low range that from 0.1 to 100μv in and its bandwidth range from 1Hz to 100 Hz. So the signal has amplified by using linear and accurate digital program amplifier(PGA).This amplifier has been designed by using First stage amplifier with gain of 120dB with low output noise. The PGA is consists of OPAMPs the PGA change from 10 dB to 120dB.Inorde to optimized the linear and gain accuracy a new structure resister array is proposed high gain PGA. Hence the simulated result has shown it is promising to exhibit an amplifier with high performance biomedical application.
Volume: 8
Issue: 2
Page: 124-129
Publish at: 2019-07-01

Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor

10.11591/ijres.v8.i2.pp81-85
R. Palanisamy , K. Vijayakumar
This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.
Volume: 8
Issue: 2
Page: 81-85
Publish at: 2019-07-01

Local mean based adaptive thresholding to classify the cartilage and background superpixels

10.11591/ijeecs.v15.i1.pp211-220
Hong Seng Gan , Bakhtiar Al-Jefri Adb Salam , Aida Syafiqah Ahmad Khaizi , Muhammad Hanif Ramlee , Wan Mahani Wan Mahmud , Yeng-Seng Lee , Khairil Amir Sayuti , Ahmad Tarmizi Musa
Semi-automatic segmentation is common in medical image processing because anatomical geometries demonstrated by human anatomical parts often requires manual supervision to provide desirable results. However, semi-automatic segmentation has been infamous for requiring excessive human intervention and time consuming. In order to reduce a forementioned problems, seed labels have been generated automatically using superpixels in our previous works. A fixed threshold method has been implemented to classify cartilage and background superpixels but this method is reported to lack the adaptiveness to changing image properties in 3D magnetic resonance image of knee. As a result, the coverage of background seeds are not sufficient to cover whole background area in some cases. In this work, we proposed a local mean based adaptive threshold method as a better alternative to the fixed threshold method. We calculated local mean for each block in an integral image and then use it to differentiate background superpixels from cartilage superpixels. The method is robust to illumination changes and simple to use. We tested the adaptive threshold on 35 knee images of different anatomical geometries and proved the proposed method could provide more comprehensive background seed labels distribution compared to fixed threshold method
Volume: 15
Issue: 1
Page: 211-220
Publish at: 2019-07-01

Integration testing based on indirect interaction for embedded system

10.11591/ijres.v8.i2.pp86-98
Muhammad Iqbal Hossain , Woo Jin Lee
Embedded systems comprise several modules that exchange data by interacting among themselves. Exchanging wrong resource data among modules may lead to execution errors or anomalies. Interacting resources produce dependencies between two modules where any change of resources by one module affects the functionality of another module. Several investigations of the embedded system such as aerospace or automobile system show interaction faults between modules are one of the major cause of critical software failures. Therefore, interaction testing is an essential phase to reduce the interaction faults and minimize the risk. The direct and indirect interaction between modules generates interaction faults where indirect interaction is made underneath the interface in which data dependence relationship with resources may cause a different outcome. We investigate errors based on the indirect interaction between modules and introduce a new test criterion for finding errors detectable by existing approaches in unit level but not in integration level. In this paper, we propose a noble approach to generate an interaction model using indirect interaction pattern and design test criteria based on different interaction errors to generate test cases. Finally, we use fault injection and data flow coverage techniques to evaluate the feasibility and effectiveness of our approach
Volume: 8
Issue: 2
Page: 86-98
Publish at: 2019-07-01

Performance optimization of task intensive real time applications on multicore ECUs - a hybrid scheduler

10.11591/ijres.v8.i2.pp114-123
Geetishree Mishra , Rajeshwari Hegde
In the current approach of Automotive electronic system design, the multicore processors have prevailed to achieve high computing performance at low thermal dissipation. Multicore processors offer functional parallelism that helps in meeting the safety critical requirements of vehicles. The number of ECUs in high-end cars could be reduced by conglomerating more functions into a multicore ECU. AUTOSAR stack has been designed to support the applications developed for multicore ECUs. The real challenges lie in adapting new design methods while developing sophisticated applications with multicore constraints. It is imperative to utilize the most of multicore computational capability towards enhancing the overall performance of ECUs. In this context the scheduling of the real time multitasking software components by the operating system is one of the key issues to be addressed. In this paper, the state of the art scheduling algorithm is reviewed and its merits and limitations are identified. A hybrid scheduler has been proposed, tested and compared with the state of the art algorithm that offers better performance in terms of CPU utilization, average response time and deadline missing rate both in normal and high load conditions.
Volume: 8
Issue: 2
Page: 114-123
Publish at: 2019-07-01

Low power and high performance FFT with different radices

10.11591/ijres.v8.i2.pp99-106
Md. Zakir Hussain , Kazi Nikhat Parvin
FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.
Volume: 8
Issue: 2
Page: 99-106
Publish at: 2019-07-01

Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology

10.11591/ijres.v8.i2.pp107-113
S.Tamil Selvan
This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.
Volume: 8
Issue: 2
Page: 107-113
Publish at: 2019-07-01

Resolving of optimal fractional PID controller for DC motor drive based on anti-windup by invasive weed optimization technique

10.11591/ijeecs.v15.i1.pp95-103
Badriyah Ahmed Obaid , Ameer Lateef Saleh , Abbas Kareem Kadhim
This paper exhibits a design procedure for tuning the parameters of Fractional Order Proportional Integral Derivative (FOPID) P  controller to optimize the DC motor drive operation. The optimization technique is establishing on Invasive Weed Optimization (IWO). This paper also proposes the use of anti-windup aspect to against the saturation which may occur in the FOPID controller. The objective of this design is to improve the performance of the drive subjected to different transient response and loading conditions. A comparative study is carried out with a classical PID controller. The Matlab simulation results show more improvements in the proposed system.
Volume: 15
Issue: 1
Page: 95-103
Publish at: 2019-07-01

Notice of Retraction: Implement embedded controller using FPGA chip

10.11591/ijres.v8.i2.pp130-144
Haresh Pandya , Mahesh Rangapariya , Jitendra Rajput
This article has been retracted by the publisher.Notes: Notice of Retraction: After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles. We hereby retract the content of this paper. Reasonable effort should be made to remove references to this paper. The presenting author of this paper has the option to appeal this decision by contacting info@iaesjournal.com.------------------------------------The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.
Volume: 8
Issue: 2
Page: 130-144
Publish at: 2019-07-01

Neuronal logic gates realization using CSD algorithm

10.11591/ijres.v8.i2.pp145-150
Lakshmi kiran Mukkara , K.Venkata Ramanaiah
Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial neural networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.
Volume: 8
Issue: 2
Page: 145-150
Publish at: 2019-07-01

Design and analysis of dual band integrated hexagonal shaped microstrip UWB antenna

10.11591/ijeecs.v15.i1.pp294-299
Alaa Farhood , Maham Kamil Naji , Suhad Hasan Rhaif Hasan Rhaif , Adnan Ali
In this paper, we proposed a hexagonal shaped microstrip ultra-wideband (UWB) antenna integrated with dual band applications. The antenna design consists of a hexagonal shape patch with two folded Capacitive Loaded Line Resonators (CLLRs) on the left edge of the patch antenna. This hexagonal structure is used to implement UWB applications (3.1-10.6 GHz). A rectangular ground, and two CLLR are also used on the bottom of antenna to obtain the extra dual resonant frequency at 2.4 GHz and 9.1 GHz for Bluetooth and radar applications respectively. The proposed design is implemented using FR4 epoxy substrate. The relative permittivity of the substrate is 4.4. The overall size of designing antenna is 26 × 30 mm2 with 1.6 mm as thickness and fed by standard feed line of 50 Ω microstrip. The results obtained from the simulation indicate that the designed antenna attains a good bandwidth from 1.1 GHz – 10.69 GHz with VSWR < 2 and return loss < -10 dB. The proposed geometry is simulated  by using the Ansoft HFSS simulator working on the principle of FEM and results are also analyzed.
Volume: 15
Issue: 1
Page: 294-299
Publish at: 2019-07-01

Development of portable automatic number plate recognition (ANPR) system on Raspberry Pi

10.11591/ijece.v9i3.pp1805-1813
S. Fakhar A. G , M. Saad H , A. Fauzan K , R. Affendi H. , M. Aidil A.
ANPR system is used in automating access control and security such as identifying stolen cars in real time by installing it to police patrol cars, and detecting vehicles that are overspeeding on highways. However, this technology is still relatively expensive; in November 2014, the Royal Malaysian Police (PDRM) purchased and installed 20 units of ANPR systems in their patrol vehicles costing nearly RM 30 million. In this paper a cheaper alternative of a portable ANPR system running on a Raspberry Pi with OpenCV library is presented. Once the camera captures an image, image desaturation, filtering, segmentation and character recognition is all done on the Raspberry Pi before the extracted number plate is displayed on the LCD and saved to a database. The main challenges in a portable application include crucial need of an efficient code and reduced computational complexity while offering improved flexibility. The performance time is also presented, where the whole process is run with a noticeable 3 seconds delay in getting the final output.
Volume: 9
Issue: 3
Page: 1805-1813
Publish at: 2019-06-01

Permanent magnet flux switching motor technology as a solution for high torque clean electric vehicle drive

10.11591/ijpeds.v10.i2.pp575-584
Enwelum I. Mbadiwe , Erwan Sulaiman , Zarafi Md. Ahmad , M.F. Omar
A breakthrough in this century has been the development of electric vehicle which is propelled by electric motor powered by electricity. Already, many electric motors have been used for electric vehicle application but performances are low. In this paper, a permanent magnet motor technology using unconventional segmented rotor for high torque application is presented. Unlike conventional motors, this design, flux switching motor (FSM) is an advance form of synchronous machine with double rotating frequency. It accommodates both armature winding and flux source on the stator while the rotor is a simple passive laminated sheet steel. Conventionally, rotor of the maiden FSM and many emerging designs have focused on the salient pole, this design employs segmented rotor. Segmented rotor has advantages of short flux path more than salient rotor pole resulting in high flux linkage. Geometric topology of the proposed motor is introduced. It consists of 24Stator-14Pole using PM flux source with alternate stator tooth armature winding. The 2D-FEA model utilized JMAG Tool Solver to design and analyze motor’s performance in terms of torque with average torque output of 470Nm. The suitability of segmented outer-rotor FS motor as a high torque machine, using permanent magnet technology is a reliable candidate for electric vehicle.
Volume: 10
Issue: 2
Page: 575-584
Publish at: 2019-06-01

EDM process through mathematical model

10.11591/ijpeds.v10.i2.pp874-881
Dana Dehghani , Azli Yahya , Nor Hisham Khamis , Ali Idham Alzaidi
EDM is a well-established hole machining option with various advantages due to non-contact characteristics of the process. However, knowledge about the process is not enough for its more improvements. Exprimenal studies are costly and time consuming because of the complex nature of process. Therefore, process modeling is a good alternative to reduce the experimental expense related to the technology. This paper studys EDM process through mathematical model, which includes the precise insight into the interactive behavior of EDM system. The ignition, discharge and recovery phases of the model have been developed through MATLABs time domain analysis. Simulation result shows good agreement with expected profile of EDM spark. To verify the model, simulated material removal rates (MRRs) from series of simulation are compared with the experimental ones reported by previous researcher. Ability of the model to predict the dynamic behavior profile of the EDM system is successfully confirmed by low average percentage error in predicting MRR.
Volume: 10
Issue: 2
Page: 874-881
Publish at: 2019-06-01

Data cryptography based on musical notes on a fingerboard along with a dice

10.11591/ijeecs.v14.i3.pp1286-1290
Asis Kumar Tripathy , Tapan Kumar Das , Navaneethan C
The security of an online system is the foremost necessity nowadays. With huge growth of the IT power and with the invention of new technologies, the number of threats a user faces is growing exponentially. Cryptography is a combination of security engineering and mathematics. It is the best technology for securing distributed systems. Cryptography consists in processing plain information by applying a cipher and producing encoded output, unknown to a third-party who does has no idea about the key. In cryptography both encryption and decryption phase are processed by one or more keys. Encryption is extremely important for a safe and secure environment for the computers and the Internet.
Volume: 14
Issue: 3
Page: 1286-1290
Publish at: 2019-06-01
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