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28,188 Article Results

ARM9-Linux Karnel

10.11591/ijres.v5.i1.pp49-56
Pradip Ram Selokar
ARM9 supports the Linux Kernel. On a development system it is advantageous to load the Root File System (RFS) through Network File System (NFS). Several pieces of software are involved to boot a linux kernel on SAM9 products. First is the ROM code which is in charge to check if a valid application is present on supported media (FLASH, DATAFLASH, NANDFLASH, and SDCARD).
Volume: 5
Issue: 1
Page: 49-56
Publish at: 2016-03-01

An Automated Way of Baking Process for Moisture Sensitive Components

10.11591/ijres.v5.i1.pp1-7
A. Ramamoorthy , M. Jagadeeshraja , L. Manivannan , K. Raja
The objective of my project is to the new technology termed as “baking process” to remove the moisture content available in the particular electronics devices which is used in Rea time industrial application. In Industries there are certain policies are maintained for semiconductor devices, which referred as “Shelf life” of the material. Once it crossed its lifetime, some process need to done to extend this. Depends on the moisture sensitive characteristics baking is employed mainly to shelf life extension. The Baking is the process of removing of moisture content from particular semiconductor device in order to effective usage in the production line.  In my propose method the moisture content is measured by corresponding moisture sensor. If it is normal level the processor goes to the normal state, If it is reaches the abnormal level (presence of moisture) the processor baked the product. Temperature and humidity sensors are effectively monitor and provide the signal to the processor. The UTLP kit provide the information about the status of the product.
Volume: 5
Issue: 1
Page: 1-7
Publish at: 2016-03-01

HW SW Co-design of Adaptive Task Scheduler for Real Time Systems

10.11591/ijres.v5.i1.pp57-68
Dinesh G Harkut
In embedded system, a real-time operating system (RTOs) is often used to structure the application code and ensure that the deadlines are met by reacting on events in the environment by executing the functions within precise time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical metrics. Generally RTOs are implemented in software, which in turns increases computational overheads, jitter and memory footprint which can be reduced even if not remove completely by utilizing latest FPGA technology, which enables the implementation of a full featured and flexible hardware based RTOs. Scheduling algorithms play an important role in the design of real-time systems. This paper proposes the novel FIS based adaptive hardware task scheduler for multiprocessor systems that minimizes the processor time for scheduling activity which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses feedback which allows processors share of task running on multiprocessor to be controlled dynamically at runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of total task and thus improves efficiency of the entire real-time system. The increased computation overheads resulted from proposed model can be compensated by exploiting the parallelism of the hardware as being migrated to FPGA
Volume: 5
Issue: 1
Page: 57-68
Publish at: 2016-03-01

Design and Analysis of CMOS and Adiabatic 1:16 Multiplexer and 16:1 Demultiplexer

10.11591/ijres.v5.i1.pp8-17
K. Anitha , R. Jayachira
Conventional CMOS is compared with two adiabatic logic styles namely Efficient Charge Recovery Logic (ECRL) and Improved Efficient Charge Recovery Logic (IECCRL). A 16:1 multiplexer and 1:16 demultiplexer using these design techniques are designed and results are compared based on their minimum/maximum power consumption and transistor count. The proposed schematics multiplexer and demultiplexer are simulated using Microwind2 and DSCH2 software.
Volume: 5
Issue: 1
Page: 8-17
Publish at: 2016-03-01

Survey on Performance and Energy consumption of Fault Tolerance in Network on Chip

10.11591/ijres.v5.i1.pp69-74
B. Naresh Kumar Reddy , Vasantha M.H , Nithin Kumar Y.B.
Network on Chip (NoC) is a communication subsystem, which has the logic for sending and receiving the data from different sources in a single IC, is adopting the technology of VLSI making it to be as compact as possible. However, the increasing probability of failures in NoC’s has been raising concern among the researchers due to large scale integration of components. In specific the issues of fault-tolerance, increase in length of global wires of NoC has to be addressed for on chip and multi core architectures. This survey presents a perspective on existing NoC Fault-tolerant algorithm and a Corresponding distributed fault analysis strategy that encourages in observing the fault status of individual NoC components and their adjacent communication links. The analysis of the Fault-tolerant Network subjected to dynamic workloads for large scale applications is also equally important. This research paper mainly emphasizes on Fault tolerant NoC strategies summarizing over thirty research papers.
Volume: 5
Issue: 1
Page: 69-74
Publish at: 2016-03-01

Information Security Risk Assessment Based on Analytic Hierarchy Process

10.11591/ijeecs.v1.i3.pp656-664
Ming Xiang He , Xin An
Information security risk assessment was an important component of information systems security engineering and the selection of assessment method had a direct impact on the final results of the assessment. But there were too many elements in the process of information security risk assessment. How to find the optimal elements from many elements to simplify the calculation of risk value and provide a strong basis for taking relevant measures, which was a problem needed to be solved. In addition, the reliability of the risk assessment results could not be guaranteed only through a single qualitative or quantitative assessment method. By Analytic Hierarchy Process (AHP), the relative weight of elements related to information security risk could be calculated. Then the optimal indicators, which provided a strong basis for taking relevant measures, could be selected by sorting the weights of elements to reduce the number of indicators. Moreover, Analytic Hierarchy Process, a method of the combination of qualitative and quantitative assessment methods, could overcome the shortcomings of single qualitative or quantitative assessment method.
Volume: 1
Issue: 3
Page: 656-664
Publish at: 2016-03-01

Preventing Online Social Deception using Deception Matrix

10.11591/ijai.v5.i1.pp35-40
Alka Alka , Harjot Kaur
The organization collaboration is very important for the success of the organization. The persons who enter into the organization will interact with the other members of the organization. There exist leaders of the community who will be responsible for the management of the communication among the persons within the organization. Sometimes the information presented by the new person joining the community is not correct. That information will cause the deception over the network. In the purposed paper deception within the social media is going to be analyzed. Deception will cause legion of problems and sometimes death of the person who is deceived. The proposed paper suggests the mechanism for tackling such deceptions.
Volume: 5
Issue: 1
Page: 35-40
Publish at: 2016-03-01

Comparison of PI and PID Controlled Bidirectional DC-DC Converter Systems

10.11591/ijpeds.v7.i1.pp56-65
K.C. Ramya , V. Jegathesan
This paper deals with comparison of responses of the PI and the PID controlled bidirectional DC-DC converter systems. A coupled inductor is used in the present work to produce high gain. Open loop and closed loop controlled systems with PI and PID controllers are designed and simulated using Matlab tool. The principles of operation and simulation case studies are discussed in detail. The comparison is made in terms of rise time, fall time, peak overshoot and steady state error.
Volume: 7
Issue: 1
Page: 56-65
Publish at: 2016-03-01

Fuzzy Logic Controller Based Bridgeless Isolated Interleaved Zeta Converter for LED Lamp Driver Application

10.11591/ijpeds.v7.i2.pp509-520
Thenmozhi R , Sharmeela C , Natarajan P , Velraj R
In recent times, High-Brightness Light Emitting Diodes (HB-LEDs) are developing rapidly and it is confirmed to be the future development in lighting not only because of their high efficiency and high reliability, however also because of their other exceptional features: chromatic variety, shock and vibration resistance, etc. In this paper, a Bridgeless (BL) Isolated Interleaved Zeta Converter is proposed for the purpose of reducing the diode failures or losses, the value of output ripples also gets decreased. The proposed BL isolated interleaved zeta converter operating in Discontinuous Conduction Mode (DCM) is used for controlling the brightness of LED Driver with inherent PFC at ac mains using single voltage sensor. The fuzzy logic controller (FLC) is used to adjust the Modulation Index of the voltage controller in order to improve the dynamic response of LED Lamp driver. Based on the error of converter output voltage, FLC is designed to select the optimum Modulation Index of the voltage controller. The proposed LED driver is simulated to achieve a unity power factor at ac mains for a wide range of voltage control and supply voltage fluctuations.
Volume: 7
Issue: 2
Page: 509-520
Publish at: 2016-02-13

Control of Power and Voltage of Solar Grid Connected

10.11591/ijece.v6i1.pp26-33
Boucetta Abd Allah , Labed Djamel
Renewable energy is high on international agendas. Currently, grid-connected photovoltaic systems are a popular technology to convert solar energy into electricity. Control of power injected into the grid, maximum power point, high efficiency, and low total harmonic distortion of the currents injected into the grid are the requirements for inverter connection into the grid. Consequently, the performance of the inverters connected to the grid depends largely on the control strategy applied. In this paper the simulation and design of grid connected three phase photovoltaic system using Matlab/Simulink has examined. The proposed system consists photovoltaic panels, boost and inverter the PV system convert the sun irradiation into direct current, thereafter we have used a boost to track the maximum power point of the PV system, three-phase inverter and LC output filter. A VOC control strategy based on the phase shifting of the inverter output voltage with respect to the grid voltage. The proposed control strategy requires few hardware and computational resources. As a result, the inverter implementation is simple, and it becomes an attractive solution for low power grid connected applications.
Volume: 6
Issue: 1
Page: 26-33
Publish at: 2016-02-01

Prolonging the Lifetime of Wireless Sensor Networks using LPA-star Search Algorithm

10.11591/ijeecs.v1.i2.pp390-398
Ahmed A. Alkathmawee , Lusong Feng , Imad S. Alshawi
Since sensors have limited power resources, energy consumption has become a critical challenge to Wireless Sensor Networks (WSNs). Most of the routing protocols proposed to transmit data packets through paths which consume low energy aim simply to reduce battery power consumption. This can lead to lead to network partition and reduce network lifetime.Therefore, to balance energy consumption and extend network lifetime while minimizing packet delivery delay; this paper proposes a new energy-routing protocol using the lifelong planning A-star (LPA-star) search algorithm. This algorithm is used to find an optimum forwarding path between the source node and the sink. The optimum path can be selected depending on highest residual sensor energy, the shortest distance to the sink and lowest traffic load. Simulation results indicate that the proposed protocol increased the lifetime of the network compared with the A-star routing (EERP) protocol.
Volume: 1
Issue: 2
Page: 390-398
Publish at: 2016-02-01

Identification of Nonlinear Systems Structured by Wiener-Hammerstein Model

10.11591/ijece.v6i1.pp167-176
A Brouri , S Slassi
Wiener-Hammerstein systems consist of a series connection including a nonlinear static element sandwiched with two linear subsystems. The problem of identifying Wiener-Hammerstein models is addressed in the presence of hard nonlinearity and two linear subsystems of structure entirely unknown (asymptotically stable). Furthermore, the static nonlinearity is not required to be invertible. Given the system nonparametric nature, the identification problem is presently dealt with by developing a two-stage frequency identification method, involving simple inputs.
Volume: 6
Issue: 1
Page: 167-176
Publish at: 2016-02-01

A Study on the Effect of Consumer Involvement and Affect Intensity before and after Plagiarism Suspicion on the Purchase Intention of Music Goods

10.11591/ijece.v6i1.pp268-274
Jin-Wan Jo , Mi-Hae Shin , Young-Chul Kim
This study aims to examine the effect of consumers' involvement and affect intensity on the purchase intention of music items. In particular  domestically, there is no clear standard for judgment of plagiarism, and thus it is expected that plagiarism suspicion is likely to affect consumers' involvement and affect intensity, and as a result, their purchase intention as well. Accordingly, consumer characteristics (involvement, affect intensity) were chosen as independent variables, and consumers' purchase intention on music items as a subordinate variable, respectively. The first questionnaire-based survey was conducted before the awareness of plagiarism suspicion, followed by the second survey after the awareness of plagiarism suspicion. It turned out that the higher level of involvement and affect intensity, both of which are consumer characteristics, the higher level of purchase intention of music goods. While plagiarism suspicion caused C.R values to decrease in every item, a significant difference was observed only in the relation of ‘involvement - purchase intention’. This study shows that music items which involve plagiarism suspicion result in changes in consumers' purchase intention, which will cause damage to the creators and performers of related music items. Thus, for the development of the music industry and creative activity, tools and standards that can clearly distinguish plagiarism need to be developed.
Volume: 6
Issue: 1
Page: 268-274
Publish at: 2016-02-01

Augmented Reality Navigation System on Android

10.11591/ijece.v6i1.pp406-412
Chee Oh Chung , Yilun He , Hoe Kyung Jung
With the advent of the Android system, smart phones are rapidly developing and through the conveniency of accessing internet on the smart phones, a user’s location information can be accessed anywhere and anytime easily. Augmented Reality Based Technology enables the provision of variety information such as pictures and location of buildings in the navigation field. Most of the augmented reality program used to Visual Trace Method (Marker method and Markerless Method). For the Visual Trace Method, the marker installation and digital information should be assigned while the Non-visual Trace Method requires the use of hardware (G.P.S, sensors etc). Most navigation systems can only show the path from a user’s current location to their destination. In this paper, the design and implementation of an augmented reality program is discussed. It will use the smart phone’s inbuilt camera and GPS to display a user’s surround information in real time on the smart phone. The proposed system will combine the G.P.S location-based technology and virtual trace technology to provide the user with basic information about a building they are looking for or one in their immediate surrounding.
Volume: 6
Issue: 1
Page: 406-412
Publish at: 2016-02-01

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

10.11591/ijece.v6i1.pp90-98
Veepsa Bhatia , Neeta Pandey , Asok Bhattacharyya
A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.
Volume: 6
Issue: 1
Page: 90-98
Publish at: 2016-02-01
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