Articles

Access the latest knowledge in applied science, electrical engineering, computer science and information technology, education, and health.

Filter Icon

Filters article

Years

FAQ Arrow
0
0

Source Title

FAQ Arrow

Authors

FAQ Arrow

29,061 Article Results

Impact of Different Time of Use Electricity Pricing Structure on Residential Consumer

10.11591/ijeecs.v10.i3.pp1053-1060
Nur Azrina Mohd Azman , Md Pauzi Abdullah , Mohammad Yusri Hassan , Dalila Mat Said , Faridah Hussin , Norzanah Rosmin , Siti Maherah Hussin
Load profile for residential users is different from commercial users where peak load occurs outside of work hours compared to working hours. Consequently, the Time of Use-based electricity price must be different not only in terms of price, but also in terms of time block structure. This paper examines the impacts of different TOU structures on TOU prices and load profiles of residential consumer. Four TOU structures are tested on the real load profile for a selected residential consumer area in Malaysia. Two elasticity factors are used for each structure to represent two different groups of users, a group that responds highly to price changes and a group that does not. The TOU price set for each structure is determined optimally subject to the following constraints; the price difference between the TOU and a fixed price per hour should be minimized and the amount of difference between price increase and price drop should be equal. From the analysis, the TOU structure with 12-time blocks provides better price signals and peak load reduction.
Volume: 10
Issue: 3
Page: 1053-1060
Publish at: 2018-06-01

Optimal Placement of FACTS Controllers for Congestion Management in the Deregulated Power System

10.11591/ijece.v8i3.pp1336-1344
S. Surender Reddy
This paper proposes a methodology to determine the optimal location of Flexible AC Transmission System (FACTS) controllers for Congestion Management (CM) in the restructured electrical power system. An approach to find the optimum placement of Thyristor Controlled Phase Angle Regulators (TCPAR) and Thyristor Controlled Series Compensators (TCSC) has been proposed in this paper. The proposed methodology is based on the sensitivity of transmission loss which a controller is installed. The total system losses and the power flows are considered as the performance indices. The traditional optimal power flow (OPF) problem is modified to include the market players, who will compete and trade simultaneously, ensuring the system operation stays within the security limits. In this paper, pool and bilateral contracts are considered. Here, an integrated methodology is proposed that includes the FACTS Controllers in a bilateral contract framework to maintain the system security and to minimize the deviations from the contractual requirements. The simulation results on IEEE 30 bus system show that the sensitivity factors could be used effectively for the optimal location of FACTS controllers in response to the required objectives.
Volume: 8
Issue: 3
Page: 1336-1344
Publish at: 2018-06-01

Selection and Validation of Mathematical Models of Power Converters using Rapid Modeling and Control Prototyping Methods

10.11591/ijece.v8i3.pp1551-1568
Fredy Edimer Hoyos , John Edwin Candelo , John Alexander Taborda
This paper presents a methodology based on two interrelated rapid prototyping processes in order to find the best correspondence between theoretical, simulated, and experimental results of a power converter controlled by a digital PWM. The method supplements rapid control prototyping (RCP) with effective math tools to quickly select and validate models of a controlled system. We show stability analysis of the classical and two modified buck converter models controlled by zero average dynamics (ZAD) and fixed-point induction control (FPIC). The methodology consists of obtaining the mathematical representation of power converters with the controllers and the Lyapunov Exponents (LEs). Besides, the theoretical results are compared with the simulated and experimental results by means of one- and two-parameter bifurcation diagrams. The responses of the three models are compared by changing the parameter K_s of the ZAD and the parameter N of the FPIC. The results show that the stability zones, periodic orbits, periodic bands, and chaos are obtained for the three models, finding more similarities between theoretical, simulated, and experimental tests with the third model of the buck converter with ZAD and FPIC as it considers more parameters related to the losses in different elements of the system. Additionally, the intervals of the chaos are obtained by using the LEs and validated by numerical and experimental tests
Volume: 8
Issue: 3
Page: 1551-1568
Publish at: 2018-06-01

Ant Based Cross Layered Optimization Protocol for Wireless Multimedia Sensor Network with Fuzzy Clustering

10.11591/ijeecs.v10.i3.pp1303-1309
Dipali Parag Adhyapak , Sridharan Bhavani , Aparna Pradeep Laturkar
Wireless Multimedia Sensor Network (WMSN) is embedded with large number of Audio, Video and scalar sensor nodes which can able to retrieve the multimedia information from the environment. WMSN has several challenges such as life time of the network, Memory requirement, Coverage, Bandwidth and QoS metrics. Hence selection of routing algorithm is crucial in WMSN. Again interdependencies of the protocol layer cannot be neglected to improve the network performance. Clustering in WMSN is challenging task in order to increase network lifetime and to improve the communication. Hence Fuzzy clustered Ant based cross layer protocol (FCAXL) is proposed. In this paper performance analysis of ant based cross layer optimization protocol with fuzzy clustering based on number of nodes and packet size is done. Simulation results shows that Fuzzy clustered ant based cross layer optimization protocol performs best as compared to AntSenseNet routing protocol, Cross layer routing protocol and Ant based cross layer routing protocol in terms of QoS parameters such as Throughput, Packet delivery ratio and delay. Hence the life time of the network increases.
Volume: 10
Issue: 3
Page: 1303-1309
Publish at: 2018-06-01

Development of Compact Pulse Generator with Adjustable Pulse Width for Pulse Electric Field Treatment Technology

10.11591/ijpeds.v9.i2.pp889-896
Nur Faizal Kasri , Mohamed Afendi Mohamed Piah
The pulse generator which has been implemented in the pulse electric field (PEF) treatment system for food processing is worth to be highlighted and improved. It is parallel with the advancement in semiconductor technology, which offers robust and accurate devices. This research is an effort to produce a low cost, compact and reliable pulse generator as well as equipped with a pulse width modulation (PWM) method for wide selection of frequency and duty cycle. The result shows that the simulation process has proven the theoretical concept to be right and yields the desired outcome based on the designed values. Then, the actual printed circuit board (PCB) has been fabricated to obtain practical results which intended to be compared with the simulation outcomes. Concerning the frequency and its duty cycle, both parameters can be altered without affecting each other. It means by changing the frequency, duty cycle remains the same and vice versa. Thus, this proposed pulse generator achieves its objective and fits to be implemented in PEF treatment technology. It also can replace the conventional pulse forming network (PFN) which is bulky and costly.
Volume: 9
Issue: 2
Page: 889-896
Publish at: 2018-06-01

Anaphora Resolution in Business Process Requirement Engineering

10.11591/ijece.v8i3.pp1766-1773
Riad Sonbol , Ghaida Rebdawi , Nada Ghneim
Anaphora resolution (AR) is one of the most important tasks in natural language processing which focuses on the problem of resolving what a pronoun, or a noun phrase refers to. Moreover, AR plays an essential role when dealing with business process textual description, either when trying to discover the process model from the text, or when validating an existing model. It helps these systems in discovering the core components in any process model (actors and objects).In this paper, we propose a domain specific AR system. The approach starts by automatically generating the concept map of the text, then the system uses this map to resolve references using the syntactic and semantic relations in the concept map. The approach outperforms the state-of-the art performance in the domain of business process texts with more than 73% accuracy. In addition, this approach could be easily adopted to resolve references in other domains.
Volume: 8
Issue: 3
Page: 1766-1773
Publish at: 2018-06-01

R&D of Photovoltaic Thermal (PVT) Systems: an Overview

10.11591/ijpeds.v9.i2.pp803-810
Ahmad Fudholi , Kamaruzzaman Sopian
Photovoltaic thermal (PVT), which is the popular technology for harvesting solar energy, receive solar energy and convert it into electrical and thermal energy simultaneously. In this review, design, heat transfer, energy modelling and performance analysis of PVT systems are presented. Four types of PVT systems base on heat transfer medium; air-based PVT system, water-based PVT system, the combination of water/air-based PVT system, and nanofluid-based PVT system are presented. In addition, major finding on energy and exergy analysis of PVT systems are summarized. 
Volume: 9
Issue: 2
Page: 803-810
Publish at: 2018-06-01

Improving Voltage Profile of Islanded Microgrid using PI Controller

10.11591/ijece.v8i3.pp1383-1388
Sajid Hussain Qazi , Mohd Wazir Mustafa
In islanding operating mode of microgrid, the voltage and frequency of system must be maintained by the microgrid, or else the system will crumble due to the characteristics of different distributed generators (DG) utilized in microgrid. The voltage and frequency lost provision when main grid is disconnected. This paper presents PI controller based voltage controller to regulate voltage to its normal condition. The controller is proposed to be utilized individually with each distributed generator (DG) in microgrid. The controller compares inverter output voltage with voltage at point of common coupling (PCC) and its output is feed to PWM pulse generator to generate appropriate pulses for inverter to regulate voltage to its nominal value. The simulation results of proposed system are shown using MATLAB/Simulink platform.
Volume: 8
Issue: 3
Page: 1383-1388
Publish at: 2018-06-01

Development of Automatic Mixing Process for Fertigation System in Rock Melon Cultivation

10.11591/ijece.v8i3.pp1913-1919
Muhammad Khairie Idham Abd Rahman , Salinda Buyamin , M. S. Zainal Abidin , Musa Mohd Mokji
This work proposed an automatic mixing system of nutrient solution for rock melon fertigation according to the required electrical conductivity (EC) level. Compared to the manual practice, this automatic system will ensure continuous supply of mixed nutrient solution without the need to daily check and mix new nutrient. Thus, this easy to use and low cost automatic system will reduce the burden of the farmers. This system uses an EC sensor to automatically check the concentration level of the mixed nutrient solution. Other than that, the system only consists of electronic pumps for mixing process and an Arduino board as the controller. The controller will monitor the EC level and run the mixing process when the EC level is below the required level. By calibrating the EC sensors, the test shows that the automatic mixing system is able to accurately keep the mixed nutrient solution concentration in a 400 L mixing reservoir at several required levels.
Volume: 8
Issue: 3
Page: 1913-1919
Publish at: 2018-06-01

Mutual Coupling Reduction between Asymmetric Reflectarray Resonant Elements

10.11591/ijece.v8i3.pp1882-1886
M. Hashim Dahri , M. H. Jamaluddin , M. Inam , M. R. Kamarudin
A physically asymmetric reflectarray element has been proposed for wide band operations. The dual resonant response has been introduced by tilting one side of the square path element. The numerical results have been analyzed in the frequency band between 24GHz to 28GHz where a reflection phase range of more than 600° has been achieved. The proposed asymmetric element can produce mutual coupling with adjacent elements on a reflectarray. This effect has been monitored by placing the elements in a mirror configuration on the surface of reflectarray. The single unit cell element results have been compared with conventional 4 element unit cell and proposed mirroring element configuration. The proposed mirroring element technique can be used to design a broadband reflectarray for high gain applications.
Volume: 8
Issue: 3
Page: 1882-1886
Publish at: 2018-06-01

Artificial Intelligence Control Applied in Wind Energy Conversion System

10.11591/ijpeds.v9.i2.pp571-578
Arama Fatima Zohra , Bousserhane Ismail Khalil , Laribi Slimane , Sahli Youcef , Mazari Benyounes
The objective of this paper is to study the dynamic response of the wind energy conversion system (WECS) based on the Doubly Fed Induction Generator (DFIG). The DFIG rotor is connected to the grid via a converter. The active and reactive power control is realized by the DFIG rotor variables control, using the field oriented control (FOC). The vector control of DFIG is applied by the use of tow regulators PI and the neural network regulator (NN). The generator mathematical model is implemented in Matlab/ Simulink software to simulate a DFIG of 1.5 MW in order to show the efficiency of the performances and robustness of the studied control systems. The simulation obtained results shows that the robustness and response time of the neural network regulator is better than those obtained by the PI classical regulator.
Volume: 9
Issue: 2
Page: 571-578
Publish at: 2018-06-01

FPGA Implementation of High Speed Hardware Efficient Carry Select Adder

10.11591/ijres.v7.i1.pp43-47
Saravanakumar Saravanakumar , Vijeyakumar Vijeyakumar , Sakthisudhan Sakthisudhan
This paper presents a novel architecture for high speed and hardware efficient carry select  addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.
Volume: 7
Issue: 1
Page: 43-47
Publish at: 2018-05-30

Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator

10.11591/ijres.v7.i1.pp21-33
Sanket Dessai , Sandeep G.
This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.
Volume: 7
Issue: 1
Page: 21-33
Publish at: 2018-05-30

An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications

10.11591/ijres.v7.i1.pp12-20
Deepak Prasad , Vijay Nath
In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.
Volume: 7
Issue: 1
Page: 12-20
Publish at: 2018-05-30

Thermal Analysis of Fair Scheduling in Real-time Embedded Systems

10.11591/ijres.v7.i1.pp48-56
Tayyaba Bokhari , Sajjad Haider Shami , Farhan Haseeb
Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations.
Volume: 7
Issue: 1
Page: 48-56
Publish at: 2018-05-30
Show 1394 of 1938

Discover Our Library

Embark on a journey through our expansive collection of articles and let curiosity lead your path to innovation.

Explore Now
Library 3D Ilustration