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29,061 Article Results

Universal Automobile Headlight Control Module for High Beam Adaptation during Night Vision Travel an Embedded Design Approach

10.11591/ijres.v7.i1.pp34-42
M. Subramania Siva , G. Jeyakumar
Road accidents during night travel increases day by day and vision impairment due to high beam contributes to the majority of the total fatalities. Headlights of vehicles pose a great danger during night driving. [1] The drivers of most vehicles use high/bright beam while driving at night. This causes a discomfort to the person travelling from the opposite direction. The driver experiences a sudden glare caused due to the high intense headlight beam from the other vehicle coming towards him from the opposite direction. We are expected to dim the headlight to avoid this glare. This glare causes a temporary blindness to a person resulting in road accidents during the night. To avoid such incidents, an embedded prototype of Automatic Headlight adaptor module is proposed. This embedded module automatically switches the high beam to low beam and returns backs to high beam, thus reducing the sudden glare effect. It also eliminates the requirement of manual switching by the driver to switch back to low beam Universal Headlight adaptor module is a unique solution to achieve the above objective, the headlight intensity of the incoming vehicles causing the glare is automatically attenuated to low beam wirelessly by the nearby vehicles affected by high beam. The interconnected modules at every vehicle independently takes the decision on the head light control of the source vehicle causing the glare by evaluating various parameters like vehicle speed, current GPS location, direction of vehicle etc.
Volume: 7
Issue: 1
Page: 34-42
Publish at: 2018-05-30

Application of Inverse Perspective Mapping for Advanced Driver Assistance Systems in Automotive Embedded Systems

10.11591/ijres.v6.i3.pp150-159
Vighnesh N.T , Rachana Anil , Rohith Kumar D , Sanjana Sharvana , Rajeshwari Hegde , B S Nagabhushana
In the recent times vehicle manufactures and automotive suppliers are progressing towards building vision based subsystems for provisioning driver assistance while targeting the automotive safety critical needs. While the acquired images constitute the fundamental input for any vision based system, transforms on images become essential to derive and gain insight into certain specific features. These derived features are used and reused at multiple places for varied automotive applications. This situation warrants a scalable and flexible image processing platform for a class of automotive applications. An attempt is made in this Research work to propose architecture that, specially, includes a layer of image transformations and to implement a prototype image processing platform. Inverse Perspective Mapping (IPM), a widely used class of transforms is emphasized in the present architecture alongside other nominal transforms. Lane departure warning system is implemented on this platform for the purpose of illustration and to analyze the effectiveness of the proposed architecture
Volume: 6
Issue: 3
Page: 150-159
Publish at: 2018-05-28

Smart Assisted Vehicle for Disabled/Elderly using Raspberry Pi

10.11591/ijres.v6.i2.pp82-87
Shubham Pandey , Shubham Chandewar , Krishnamoorthy A.
Independent mobility is a key component in maintaining the physical and psychosocial health of an individual. Further, for people e having disabled/elderly, independent mobility increases vocational and educational opportunities, reduces dependence on caregivers and family members, and promotes feelings of self-reliance. Psychologically, a decrease in mobility can lead to feelings of emotional loss, anxiety, depression, educed self-esteem, social isolation, stress, and fear of abandonment. Even though the benefits of powered mobility are well documented, the safety issues associated with operation of powered vehicles often prevent clinicians and rehabilitation practitioners from prescribing powered mobility. So we are introducing an intelligent vehicle for disables/elderly people which uses an array of sensors to help with the movement of the vehicle with minimal human interaction. Functionalities of the proposed system are further enhanced using android interface connect to the vehicle via Bluetooth.
Volume: 6
Issue: 2
Page: 82-87
Publish at: 2018-05-28

Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

10.11591/ijres.v6.i1.pp36-40
G. Vadiraj , K. Shivanand , B. Sampat , G. Subramanya Nayak
Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.
Volume: 6
Issue: 1
Page: 36-40
Publish at: 2018-05-28

Simulation and Real Time Implementation of Various PWM Strategies for 3 Φ Multilevel Inverter Using FPGA

10.11591/ijres.v6.i1.pp1-19
C. R. Balamurugan , S. P. Natarajan , T. S. Anandhi , B. Shanthi
For high power applications Multilevel Inverter (MLI) is extensively used. The major advantages of MLI are good power quality, low switching losses and maintenance of the desired voltage. In this work, the three phase cascaded multi level inverter is analyzed under various modulation techniques that include Sub-Harmonic Pulse Width Modulation (SHPWM) i.e. Phase Disposition (PD) strategy, Phase Opposition Disposition (POD) strategy, Alternate Phase Opposition Disposition (APOD) strategy, hybrid strategy (PD and PS) and Phase Shift (PS) strategy. The study will help to choose those techniques with reduced harmonics for the chosen three phase cascaded MLI with R-L load. The Total Harmonic Distortion (THD), VRMS (fundamental), crest factor and form factor are evaluated for various modulation indices at two different switching frequencies (3.15KHz and 6 KHz). Simulation is performed using MATLAB-SIMULINK. It is observed that HYBRID PWM and PSPWM methods provide output with relatively low distortion for low and high switching frequencies. PODPWM and PSPWM are found to perform better since they provide relatively higher fundamental RMS output voltage for 6 KHz and 3.15 KHz switching frequencies. The experimental result shows PSPWM provide output with low distortion and HYBRID PWM provide output with higher fundamental RMS voltage for fc=3.15KHz. The experimental results were obtained only for fc=3.15KHz.
Volume: 6
Issue: 1
Page: 1-19
Publish at: 2018-05-28

Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

10.11591/ijres.v6.i3.pp160-168
G. Prasad Acharya , M. Asha Rani
This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.
Volume: 6
Issue: 3
Page: 160-168
Publish at: 2018-05-28

Metal-Embedded SU-8 Slab Techniques for Low-Resistance Micromachined Inductors

10.11591/ijres.v6.i2.pp88-96
Manot Mapato , Prapong Klysuban , Thanatchai Kulworawanichpong , Nimit Chomnawang
This work presents new fabrication technique for micro power-inductors by using metal-embedded SU-8 slab techniques. This techniques used X-ray lithography to fabricate high aspect-ratio LIGA-like micro-structures in form of embedded structure in SU-8 slab and applied for inductor’s winding fabrication with aspect-ratio of 10. Thishigh-aspect ratiostructure can provide very low resistance winding but preserve small form factor and low profile. Inductors were designed as pot-core structures with8 μm-thick permalloy core and 250 μm-thick copper winding. 4-types of inductors were fabricated including 3, 5, 10 and 16 turns in the area of 1.8 mm2 to 9.5 mm2. All inductors have overall heights of 370 μm, measured inductance value in a range of 70 nH to 1.3 μH at 1 MHz and DC resistance value of 30 mΩ to 336 mΩ for 3 turns to 16 turns respectively. From this result, high aspect-ratio inductors show good results including low-resistance, high inductance, and a small form factor as expected. 
Volume: 6
Issue: 2
Page: 88-96
Publish at: 2018-05-28

On-chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices

10.11591/ijres.v6.i1.pp41-47
Anurag Shrivastava , Sudhir Kumar Sharma
Today’s scenario of SOC deals with integrity and sharing of information or data with various level of communication. AMBA bus protocol has been proposed by ARM community to justify the uneven demand of integrity .In this paper functional description and implementation of high peripheral devices supporting protocol AXI2.0 and its interface between low peripheral devices has been proposed. The connection named as bridge take care of the protocol mismatch and operates on data transfer for uneven speed demand. Asynchronous   FIFO has been considered to avoid the complex handshaking mechanism. The design has been implemented within VHDL and implemented on Xilinx Virtex 4.
Volume: 6
Issue: 1
Page: 41-47
Publish at: 2018-05-28

MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN

10.11591/ijres.v6.i2.pp120-126
Ramesh Pawase , N.P. Futane
Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed.  A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization.  The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.
Volume: 6
Issue: 2
Page: 120-126
Publish at: 2018-05-28

FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits

10.11591/ijres.v6.i1.pp53-68
G. Durga Prasad , V Jegathesan
Multilevel converters tender advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation and have been widely accepted for high-power high-voltage applications.  This paper introduces topology in multilevel dc link inverter (MLDCLI), which can significantly reduce the switch count and improve the performance. The preferred topology provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, to the bridge inverter, which in turn gives the required alternating waveform. This topology requires fewer components compared to traditional Multi level Inverters (MLI).Therefore, the overall cost and complexity are significantly reduced particularly for higher output voltage levels. Finally, Matlab/Simulink and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. Simulation and experimental results for fifteen-level inverter are presented for validation.
Volume: 6
Issue: 1
Page: 53-68
Publish at: 2018-05-28

FPGA-based Architecture of Direct Torque Control

10.11591/ijres.v6.i1.pp20-27
Azaza Maher , Echaieb Kamel , Mami Abdelkader
This paper presents an optimized FPGA architecture of a DTC “direct torque control” drive of an induction motor. The proposed architecture is based on variable fixed point world size and the use ipcores in order to achieve higher sampling frequency which leads to reduce the electromagnetic torque and flux ripples. The hardware implementation was experimentally validated, the results shows the effectiveness of the hardware DTC drive implementation by the minimization of the torque and flux ripple
Volume: 6
Issue: 1
Page: 20-27
Publish at: 2018-05-28

Minimizing the loses of solar power generation by designing an intelligent tracking system implemented on FPGA

10.11591/ijres.v6.i3.pp169-178
Alaa Hamza Omran
The increasing of using of an electrical power as a power source in a large number of devices can occur a serious problem in our daily life. One of the useful power sources is a solar cell which used to overcome many problems of power generation. In this paper, the solar cell model is proposed to minimize loses of solar power generation by designing of an intelligent tracking system based on FPGA. PSO algorithms are used to train the neural networks to control the speeds and the directions of rotations of two DC motors with the help of FPGA cart. The proposed system was implemented in MATLAB; and for the hardware part, FPGA was used for the implementation of neural networks.
Volume: 6
Issue: 3
Page: 169-178
Publish at: 2018-05-28

CMOS Active Inductor Based Voltage Controlled Oscillator

10.11591/ijres.v6.i2.pp97-104
Dhara P Patel , Shruti Oza , Rajesh A Thakker
A Tunable Active Inductor (TAI) based Voltage Controlled Oscillator (VCO) for Radio Frequency (RF) applications ranging from 670 MHz - 1.53 GHz is presented. A design of low phase noise and compact VCO is proposed. In order to lower the phase noise of VCO, its RF output power has been improved. The use of low voltage active in-ductor circuit reduces the power dissipation of VCO. The single ended CMOS active inductors with minimum number of transistors are used to consume less die area of VCO circuit. The low power dissipation of the circuit have high efficiency to generate output RF power. A supply independent variable current source tunes the VCO. The post layout design is simulated in Cadence spectreRF using TSMC 180 nm process libraries. The VCO circuit shows the phase noise variation from -124 to  - 126 dBc/Hz and an active area of 0.0049 mm2. The VCO core circuit, excluding output buffers, consumes 10 mW at 1.8 V supply voltage.
Volume: 6
Issue: 2
Page: 97-104
Publish at: 2018-05-28

FPGA implementation of DS-CDMA Transmitter and Receiver

10.11591/ijres.v6.i3.pp179-185
Harinath Mandalapu , B Murali Krishna
Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.
Volume: 6
Issue: 3
Page: 179-185
Publish at: 2018-05-28

NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm

10.11591/ijres.v6.i2.pp105-110
A. Kalimuthu , M. Karthikeyan
A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique
Volume: 6
Issue: 2
Page: 105-110
Publish at: 2018-05-28
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