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29,734 Article Results

Prediction Outcome for Massive Multiplayer Online Games Using Data Mining

10.11591/ijeecs.v11.i1.pp248-255
Shazwani Samsurim , Nor Ashikin Mohamad Kamal , Marina Ismail , Norizan Mat Diah
Massive Multiplayer Online (MMO) game is one of the famous game genres among teenagers nowadays. MMO games allow gamers to interact and play with up to thousand players. Rainbow Six Siege (RSS) belongs to MMO type of game. However, due to many operators that are available in this game, the player needs to choose the right operator to counter the enemy operator. Therefore, based on the characteristic of the selected operator, this paper attempted to predict the outcomes of the game.  In our prediction model, characteristics for these operators were extracted from 120 live stream replays. Three classification algorithms were utilized to predict the outcome of the game. Among these algorithms, IBK had obtained outstanding performance in the dataset. The accuracy of the model is 93.75%, applying 5-fold cross-validation test. The success rate reveals that our proposed model is suitable to predict the outcome of the game.
Volume: 11
Issue: 1
Page: 248-255
Publish at: 2018-07-01

Symmetrical and Asymmetrical Multilevel Inverter Structures with Reduced Number of Switching Devices

10.11591/ijeecs.v11.i1.pp144-151
M. H. Yatim , A. Ponniran , M. A. Zaini , M. S. Shaili , N. A. S. Ngamidun , A.N. Kasiran , A. A. Bakar , J.N. Jumadril
The purpose of this study is to analyze the operation and design of symmetrical and asymmetrical multilevel inverter structures with reduced number of switching devices. In this study, the term of conventional inverter is defined as a single cascaded inverter. Specifically, the inverter operates in three complete loops and only produces 2-level and 3-level of output voltages. Usually, cascaded structure suffers from the high total harmonic distortion. Thus, by considering multilevel structure of inverter, low total harmonic distortion reduction and voltage stress reduction on switching devices can be archived. Sinusoidal pulse width modulation and modified square pulse width modulation are used as modulation techniques in switching schemes of the designed multilevel inverters. The findings indicate that, the designed multilevel structure cause low total harmonics distortion at the output voltage. Furthermore, the asymmetrical structure is producing the same output voltage levels with reduced number of switching devices compared to the symmetrical structure is experimentally confirmed. The findings show that the total harmonic distortion for 7-level (symmetrical) and 9-level (asymmetrical) are 16.45% and 15.22%, respectively.
Volume: 11
Issue: 1
Page: 144-151
Publish at: 2018-07-01

Edge detection Using Histogram Localization

10.11591/ijeecs.v11.i1.pp341-355
Mohamed Asharudeen , Hema P Menon
Detection of edges under noisy environments has been gaining lot of prominence in the recent past in most of the image and video processing applications. In this work a novel approach based on the distribution of intensity values and their corresponding positions has been proposed for distinguishing the edge pixels from the grey scale images. Separate histogram has been maintained for X and Y coordinates. The first order derivative is applied over these histograms to distinguish the edge pixels. The pixel with gradient distribution below a specific threshold value is selected as an edge pixel. This method is found to work well in case of both noiseless and noisy images. Hence this method is able to perceive the underlying information in case of noisy images also. The proposed algorithm can be used for both low and high resolution images. However, the performance of the algorithm is more evident in high resolution image. A general analysis of the proposed method has been conducted for arbitrary images. The major application of the proposed work can be used for the applications that doesn’t need any preprocessing or to avoid any loss of information like in medical image analysis as it contemplate towards every intensity bin to trace the edges present in the histogram of the image rather than the overall image concerning for direct edge tracing. The results have been compared with canny algorithm which is most commonly used for edge detection.
Volume: 11
Issue: 1
Page: 341-355
Publish at: 2018-07-01

Smart Monitoring and Controlling of Frequency Deviation by Using MATLAB GUI and ARDUINO DAQ Card

10.11591/ijeecs.v11.i1.pp224-232
Waqar Tariq , Mohammad Lutfi Othman , Noor Izzri Abdul Wahab , Shamim Akhtar
Electricity transmission and distribution in most of the countries are needed to be improved by the construction of new networks. These improvements are not that much cost effective and if cost is tried to be reduced then the quality and efficiency of the system is compromised which is not suitable at all for the current system. In addition obtaining planning permission and carrying out construction is so much difficult in busy cities. The main objective of this research is to monitor and control frequency deviation. A simple MATLAB controlling and monitoring system is being developed and the ARDUINO DAQ card is used to calculate the frequency deviation. The purpose of respective research is basically based on a dummy load which is used to show the usage of particular equipment’s used in a home such as fridge, freezer ,oven , lighting system, and domestic wet appliances such as washer dryer  which are attached these to a DAQ and then to a controlling and monitoring GUI MATLAB based. However, this research is focused on the monitoring and controlling of the frequency deviation.
Volume: 11
Issue: 1
Page: 224-232
Publish at: 2018-07-01

Robust Security for Health Information by ECC with Signature Hash Function in WBAN

10.11591/ijeecs.v11.i1.pp256-262
G. Sridevi Devasena , S. Kanmani
Wireless Body Area Networks (WBANs) are fundamental technology in health care that permits the information of a patient’s essential body parameters to be gathered by the sensors. However, the safety and concealment defense of the gathered information is a key uncertain problem. A Hybrid Key Management (HKM) scheme [13] is worked based on Public Key Cryptography (PKC)-authentication scheme. This scheme uses a oneway hash function to construct a Merkle Tree. The PKC method increase the computational complexity and lacking scalability. Additionally, it increases expensive computation, communication costs and delay. To overcome this problem, Robust Security for Protected Health Information by ECC with signature Hash Function in WBAN (RSP) is proposed. The system employs hash-chain based key signature technique to achieve efficient, secure transmission from sensor to user in WBAN. Moreover, Elliptical Curve Cryptography algorithm is used to verifies the authenticate sensor. In addition, it describes the experimental results of the proposed system demonstrate the efficient data communication in a network.
Volume: 11
Issue: 1
Page: 256-262
Publish at: 2018-07-01

A Novel Face Recognition Algorithm Using Gabor - based KPCA

10.11591/ijres.v7.i2.pp124-130
Umasankar Ch , D. Naresh Kumar , Md. Abdul Rawoof , D. Khalandar Basha , N. Madhu
The Gabor wavelets are used to extract facial features, and then a doubly nonlinear mapping kernel PCA (DKPCA) is proposed to perform feature transformation and face recognition. The conventional kernel PCA nonlinearly maps an input image into a high-dimensional feature space in order to make the mapped features linearly separable. However, this method does not consider the structural characteristics of the face images, and it is difficult to determine which nonlinear mapping is more effective for face recognition. In this work, a new method of nonlinear mapping, which is performed in the original feature space, is defined. The proposed nonlinear mapping not only considers the statistical properties of the input features, but also adopts an Eigen mask to emphasize those important facial feature points The proposed algorithm is evaluated based on the Yale database, the AR database, the ORL database and the YaleB database.
Volume: 7
Issue: 2
Page: 124-130
Publish at: 2018-07-01

Comparison of Swarm Intelligence Algorithms for High Dimensional Optimization Problem

10.11591/ijeecs.v11.i1.pp300-307
Samar Bashath , Amelia Ritahani Ismail
High dimensional optimization considers being one of the most challenges that face the algorithms for finding an optimal solution for real-world problems. These problems have been appeared in diverse practical fields including business and industries. Within a huge number of algorithms, selecting one algorithm among others for solving the high dimensional optimization problem is not an easily accomplished task. This paper presents a comprehensive study of two swarm intelligence based algorithms: 1-particle swarm optimization (PSO), 2-cuckoo search (CS).The two algorithms are analyzed and compared for problems consisting of high dimensions in respect of solution accuracy, and runtime performance by various classes of benchmark functions. 
Volume: 11
Issue: 1
Page: 300-307
Publish at: 2018-07-01

On the Review and Setup of Security Audit using Kali Linux

10.11591/ijeecs.v11.i1.pp51-59
Teddy Surya Gunawan , Muhammad Kassim Lim , Nurul Fariza Zulkurnain , Mira Kartiwi
The massive development of technology especially in computers, mobile devices, and networking has bring security issue forward as primarily concern. The computers and mobile devices connected to Internet are exposed to numerous threats and exploits. With the utilization of penetration testing, vulnerabilities of a system can be identified and simulated attack can be launched to determine how severe the vulnerabilities are. This paper reviewed some of the security concepts, including penetration testing, security analysis, and security audit. On the other hand, Kali Linux is the most popular penetration testing and security audit platform with advanced tools to detect any vulnerabilities uncovered in the target machine. For this purpose, Kali Linux setup and installation will be described in more details. Moreover, a method to install vulnerable server was also presented. Further research including simulated attacks to vulnerable server on both web and firewall system will be conducted.
Volume: 11
Issue: 1
Page: 51-59
Publish at: 2018-07-01

Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

10.11591/ijres.v7.i2.pp115-123
Nehru.K K , Nagarjuna T , Somanaidu U
Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes with the lowest transistor count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.
Volume: 7
Issue: 2
Page: 115-123
Publish at: 2018-07-01

Optimal Charging Schedule Coordination of Electric Vehicles in Smart Grid

10.11591/ijeecs.v11.i1.pp82-89
Wan Iqmal Faezy Wan Zalnidzam , Hasmaini Mohamad , Nur Ashida Salim , Hazlie Mokhlis , Zuhaila Mat Yasin
The increasing penetration of electric vehicle (EV) at distribution system is expected in the near future leading to rising demand for power consumption. Large scale uncoordinated charging demand of EVs will eventually threatens the safety operation of the distribution network. Therefore, a charging strategy is needed to reduce the impact of charging. This paper proposes an optimal centralized charging schedule coordination of EV to minimize active power losses while maintaining the voltage profile at the demand side. The performance of the schedule algorithm developed using particle swarm optimization (PSO) technique is evaluated at the IEEE-33 Bus radial distribution system in a set time frame of charging period. Coordinated and uncoordinated charging schedule is then compared in terms of active power losses and voltage profile at different level of EV penetration considering 24 hours of load demand profile. Results show that the proposed coordinated charging schedule is able to achieve minimum total active power losses compared to the uncoordinated charging.
Volume: 11
Issue: 1
Page: 82-89
Publish at: 2018-07-01

Big Data Security Architecture using Split and Merge Method

10.11591/ijeecs.v11.i1.pp268-274
Archana RA , Ravindra S Hegadi , Manjunath T N
Due to rapid growth of unstructured data in contemporary information world, there is an essence of big data infrastructure for many applications spread across domains, due to the different source information type and huge volume, data ingestion and data retrieval is important activity during this process data security is a vital to protect user data, in connection with this, authors proposed a big data security architecture using split and merge security method in big data environment using hadoop.This work will help Data security professionals and organizations implementing big data projects.
Volume: 11
Issue: 1
Page: 268-274
Publish at: 2018-07-01

A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation

10.11591/ijres.v7.i2.pp104-114
Vikas Mittal
The present work addresses the design of power efficient fully self biased OTA using a design methodology based on the  transistor characteristics. This analog module was analyzed, designed and prototyped in TSMS 0.35μm CMOS technology. Simulation results are presented, in order to validate the methodology. The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW. The results have been taken with load variations, temperature variations, and power supply variations. This circuit used in real time high frequency applications as in RF communication.
Volume: 7
Issue: 2
Page: 104-114
Publish at: 2018-06-30

Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System

10.11591/ijres.v7.i2.pp67-73
Shamim Akhter , Divya Bareja , Satyendra Kumar
Notice of Retraction-----------------------------------------------------------------------After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles.We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.The presenting author of this paper has the option to appeal this decision by contacting ijres@iaesjournal.com.-----------------------------------------------------------------------Residue Number System (RNS) is a very old number system which was proposed in 1500 AD. Parallel nature for mathematical operations in RNS results in faster computation. This paper deals with designing of modulo multiplication in RNS. Direct computation of |AB|m, requires multiplier to get A.B first and then Mod-m calculator to get the final result. We have used Vedic technique along with RNS to improve the computation time for modulo multiplication. This paper is aimed at designing and analysis of modulo multiplier for special moduli set like 3, 5 and 7. Comparative analysis in terms of area and delay is performed for input data size (N=8, 16 and 32-bit) between proposed technique and direct computation using Xilinx ISE 14.1. Design is also been compared using Synopsys Design Compiler with 32 nm Std_Cell Library. It is found that proposed technique is more efficient in terms of speed when input data size increases.
Volume: 7
Issue: 2
Page: 67-73
Publish at: 2018-06-30

Berger Code Based Concurrent Online Self-Testing of Embedded Processors

10.11591/ijres.v7.i2.pp74-81
G. Prasad Acharya , M. Asha Rani
In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults.
Volume: 7
Issue: 2
Page: 74-81
Publish at: 2018-06-30

FPGA Implementation of DTCWT and PCA Based Watermarking Technique

10.11591/ijres.v7.i2.pp82-90
M. S. Sudha , T. C. Thanuja
The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.
Volume: 7
Issue: 2
Page: 82-90
Publish at: 2018-06-30
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