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27,404 Article Results

A Robust Control with the Combination of Fuzzy and SMC to Stabilize the Power System

10.11591/ijeecs.v4.i2.pp341-353
Mohammadreza Barzegaran , Sana Tajvidi
Common power system stabilizer (CPSS), fuzzy power system stabilizer (FPSS) and sliding mode controller (SMC) are common controllers which are used in controlling single machine infinite bus (SMIB) power systems. Each of these controllers has disadvantages. CPSS is not robust enough to stabilize the power system perfectly. SMC is more robust than CPSS but in the presence of big uncertainties it is unable to stabilize power system. FPSS is enough robust in the presence of big uncertainties, but it causes chattering when high switching gain is needed. The goal of this paper is to present a robust controller for a single machine infinite bus (SMIB). The proposed controller is a direct fuzzy controller assisted with a sliding mode controller. The simulation shows clear positive effect and validity of the method in convergence, time and accuracy.
Volume: 4
Issue: 2
Page: 341-353
Publish at: 2016-11-01

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

10.11591/ijeecs.v4.i2.pp397-405
P.N. Metange , K. B. Khanchandani
This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.
Volume: 4
Issue: 2
Page: 397-405
Publish at: 2016-11-01

Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications

10.11591/ijeecs.v4.i2.pp412-423
Mahaba Saad , Khalid Youssef , Mohamed Tarek , Hala Abdel-Kader
Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6).  The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers   and  provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation  on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. 
Volume: 4
Issue: 2
Page: 412-423
Publish at: 2016-11-01

A Power Sharing Method for Parallel Inverters with Virtual Synchronous Generator Control Strategy

10.11591/ijeecs.v4.i2.pp317-324
Sara Yahia Altahir Mohamed , Xiangwu Yan
A new power sharing method of a virtual sychronous generator control based inverters is introduced in this paper. Since virtual synchronous generator has virtual inertia and damping properties, it significantly enhances the grid stability. However, its output power considerably affects by the line impedance. Thus, in this paper, the relation between the droop control and the line impedance is analyzed at first. Then, by appling an improved droop control strategy to an inverter based on the virtual sychronous generator control, achieving proportional active and reactive power sharing unaffected by the line impedance is realized. The result shows that a smooth response is achieved. As well as, the voltage drop caused by the line impedance is totally compensated. As a result, the system stability is furtherly improved. At last, the effectiveness of the proposed method is verified through MATLAB/Simulink.
Volume: 4
Issue: 2
Page: 317-324
Publish at: 2016-11-01

Determination of Unknown Parameters of Photovoltaic Module Using Genetic Algorithm

10.11591/ijeecs.v4.i2.pp271-278
I. M. Abdelqawee , Ayman Y. Yousef , Khaled M. Hasaneen , H. G. Hamed , Maged N. F. Nashed
 In this paper, the unknown parameters of the photovoltaic (PV) module are determined using Genetic Algorithm (GA) method. This algorithm based on minimizing the absolute difference between the maximum power obtained from module datasheet and the maximum power obtained from the mathematical model of the PV module, at different operating conditions. This method does not need to initial values, so these parameters of the PV module are easily obtained with high accuracy. To validate the proposed method, the results obtained from it are compared with the experimental results obtained from the PV module datasheet for different operating conditions. The results obtained from the proposed model are found to be very close compared to the results given in the datasheet of the PV module.
Volume: 4
Issue: 2
Page: 271-278
Publish at: 2016-11-01

Video Transmission using Combined Scalability Video Coding over MIMO-OFDM Systems

10.11591/ijeecs.v4.i2.pp390-396
Kalvein Rantelobo , Hendro Lami , Wirawan Wirawan
The needs of efficient bandwidth utilization and method to handle bandwidth fluctuation condition of wireless channel have become fundamental problems in video transmission. This research proposed Combined Scalable Video Coding (CSVC) that refers to Joint Scalable Video Model (JSVM), i.e. development of video coding H.264/AVC by exploiting scalable combination method using Medium Grain Scalability (MGS) on wireless channel of MIMO-OFDM (Multiple Input Multiple Output – Orthogonal Frequency Division Multiplexing) technology. The research shows that the scalable combination method can be implemented on the scenario for wireless transmission on multicast network. Experimental results show that the delivered quality is close to the alternative traditional simulcast delivery mechanism in MIMO-OFDM systems.
Volume: 4
Issue: 2
Page: 390-396
Publish at: 2016-11-01

FPGA Implementation of BCG Signal Filtering Scheme by Using Weight Update Process

10.11591/ijeecs.v4.i2.pp373-382
Manjula B.M , Chirag Sharma
A well-prepared abstract enables the reader to identify the basic content of a document quickly and accurately, to determine its relevance to their interests, and thus to decide whether to read the document in its entirety. The Abstract should be informative and completely self-explanatory, provide a clear statement of the problem, the proposed approach or solution, and point out major findings and conclusions. The Abstract should be 100 to 200 words in length. The abstract should be written in the past tense. Standard nomenclature should be used and abbreviations should be avoided. No literature should be cited. The keyword list provides the opportunity to add keywords, used by the indexing and abstracting services, in addition to those already present in the title. Judicious use of keywords may increase the ease with which interested parties can locate our article
Volume: 4
Issue: 2
Page: 373-382
Publish at: 2016-11-01

A Study on Digital Forensics in Hadoop

10.11591/ijeecs.v4.i2.pp473-478
Sachin Arun Thanekar , K. Subrahmanyam , A.B. Bagwan
Nowadays we all are surrounded by Big data. The term ‘Big Data’ itself indicates huge volume, high velocity, variety and veracity i.e. uncertainty of data which gave rise to new difficulties and challenges. Hadoop is a framework which can be used for tremendous data storage and faster processing. It is freely available, easy to use and implement. Big data forensic is one of the challenges of big data. For this it is very important to know the internal details of the Hadoop. Different files are generated by Hadoop during its process. Same can be used for forensics. In our paper our focus is on digital forensics and different files generated during different processes. We have given the short description on different files generated in Hadoop. With the help of an open source tool ‘Autopsy’ we demonstrated that how we can perform digital forensics using automated tool and thus big data forensics can be done efficiently.
Volume: 4
Issue: 2
Page: 473-478
Publish at: 2016-11-01

Design and Development of ARM based Electronic Test Evaluation System for RTO

10.11591/ijres.v5.i3.pp148-152
Shweta Salokhe , U. L. Bombale
Electronic  test  evaluation  system  for  driving  license  is  very  useful  now  a  days,  as  there  is   increase  in  the  human  intervention  in  the  system.  This  system  make  the  driving  license  procedure  transparent  to  human  being. The  proposed  technological  solution  is advancement  towards    the  automation  of  system  and  improves  the  driving  test accuracy. As  a  contribution  to  society  this system  reduces  the  number  of  road  accidents occurs due to untrained drivers.
Volume: 5
Issue: 3
Page: 148-152
Publish at: 2016-11-01

Hardware Implementation of Intrusion Detection System for Ad-Hoc Network

10.11591/ijres.v5.i3.pp153-159
Reji Mano , P.C. Kishore Raja , Christeena Joseph , Radhika Baskar
New technologies have been developed in wireless adhoc network need more security. To widespread the adhoc networks we turn in the attention of wireless hand held device mobile phones communicate with short distance using wireless lan card or Bluetooth. The performance of mobile phone are improved greatly for last few years .so security is more important for mobile networks In this paper  hardware implementation of single hop ad-hoc network is implemented and analysed using microcontroller. The protocol implemented in this paper is primarily based on, Ad hoc On-Demand Distance Vector routing. We adopt On Demand Distance Vector routing solely based on source routing and “On Demand” process, so each packet does not have to transmit any periodic routing information. We implemented   intrusion detection system with five different nodes and the performance parameters like packet delivery ratio, throughput, delay are computed with attacker and without attacker and on demand distance vector routing protocols is proposed to implement in hardware using Zigbee
Volume: 5
Issue: 3
Page: 153-159
Publish at: 2016-11-01

A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW

10.11591/ijres.v5.i3.pp160-169
B. Naresh Kumar Reddy , N. Suresh , J.V.N. Ramesh
Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.
Volume: 5
Issue: 3
Page: 160-169
Publish at: 2016-11-01

Analysis of Five-Level DSTATCOM for Harmonic Reduction in Power System Due To Non-Linear Loads

10.11591/ijeecs.v4.i2.pp286-297
N. Raveendra , V. Madhusudhan , A. Jayalaxmi
This paper deals with the elimination of harmonics at PCC in the presence of non-linear type of loads. Introduction of five-level DSTATCOM at PCC injects compensating currents for the minimization of harmonic content in the source currents. Non-linear loads when connected to the system draw non-linear components of current leaving undesired harmonics at the source side. DSTATCOM when connected to the system at the coupling point induces compensating currents to nullify harmonics. This paper introduces the simulation modelling of five-level DSTATCOM for harmonic elimination. Matlab/Simulink  modelling was done for the system without DSTATCOM and its harmonic contents were shown. The system without DSTATCOM is compared with the system with the presence of DSTATCOM showing their respective THD in the source current. Five level DSTATCOM was validated by considering fixed load and variable load. Simulation work was carried out for three types of systems and results were obtained using Matlab/Simulink.
Volume: 4
Issue: 2
Page: 286-297
Publish at: 2016-11-01

Learning Vector Quantization Image for Identification Adenium

10.11591/ijeecs.v4.i2.pp383-389
Resty Wulanningrum , Bagus Fadzerie Robby
Information and technology are two things that can not be separated and it has become a necessity for human life. Technology development at this time was not only used for intelligence purposes only, but has penetrated the world of holtikurtura. Adenium is one of the plants are much favored by ornamental plants lovers. Many of cultivation adenium who crosses that appear new varieties that have the color and shape are similar to each other. From this case, then made an application that can identify the type of adenium based on the image of that flower. Learning Vector quantization is one of the algorithm  that used for clustering. Based on test scenarios were performed, image identification applications Adenium petals produce an accuracy of 86.66% with a number of training dataset of 135 images and datasets with a test as many as 45 images max epoch 10 and learning rate between 0.01 to 0.05.
Volume: 4
Issue: 2
Page: 383-389
Publish at: 2016-11-01

An FPGA Implementation of On Chip UART Testing with BIST Techniques

10.11591/ijres.v5.i3.pp170-176
P Bala Gopal , K Hari Kishore
A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
Volume: 5
Issue: 3
Page: 170-176
Publish at: 2016-11-01

Digitalized Electronic Voting System

10.11591/ijres.v5.i3.pp143-147
Dukka Bindu Venkata Raghav , Sunith Kumar Bandi
In the present scenario, Electronic Voting Machines ("EVM") are being used in India, generally for state elections. These EVMs are being used since 1999 upto till date. The EVMs reduce the time for both casting a vote and declaring the results when compared to the old paper ballot systems, up to 2004 there is no Tampering and security provided for EVMs after 2004 Supreme court and Election Commission decided to introduce EVMs with Voter Verified Paper Audit Trail(VVPAT) system but it also having some difficulties like missing of names in the voter list, requirement of huge manpower, storing of EVMs for counting purpose etc, so our proposed method is useful to overcome above problems in the voting system by using the Biometric and Aadhaar  information.  
Volume: 5
Issue: 3
Page: 143-147
Publish at: 2016-11-01
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