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Metal-Embedded SU-8 Slab Techniques for Low-Resistance Micromachined Inductors

10.11591/ijres.v6.i2.pp88-96
Manot Mapato , Prapong Klysuban , Thanatchai Kulworawanichpong , Nimit Chomnawang
This work presents new fabrication technique for micro power-inductors by using metal-embedded SU-8 slab techniques. This techniques used X-ray lithography to fabricate high aspect-ratio LIGA-like micro-structures in form of embedded structure in SU-8 slab and applied for inductor’s winding fabrication with aspect-ratio of 10. Thishigh-aspect ratiostructure can provide very low resistance winding but preserve small form factor and low profile. Inductors were designed as pot-core structures with8 μm-thick permalloy core and 250 μm-thick copper winding. 4-types of inductors were fabricated including 3, 5, 10 and 16 turns in the area of 1.8 mm2 to 9.5 mm2. All inductors have overall heights of 370 μm, measured inductance value in a range of 70 nH to 1.3 μH at 1 MHz and DC resistance value of 30 mΩ to 336 mΩ for 3 turns to 16 turns respectively. From this result, high aspect-ratio inductors show good results including low-resistance, high inductance, and a small form factor as expected. 
Volume: 6
Issue: 2
Page: 88-96
Publish at: 2018-05-28

On-chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices

10.11591/ijres.v6.i1.pp41-47
Anurag Shrivastava , Sudhir Kumar Sharma
Today’s scenario of SOC deals with integrity and sharing of information or data with various level of communication. AMBA bus protocol has been proposed by ARM community to justify the uneven demand of integrity .In this paper functional description and implementation of high peripheral devices supporting protocol AXI2.0 and its interface between low peripheral devices has been proposed. The connection named as bridge take care of the protocol mismatch and operates on data transfer for uneven speed demand. Asynchronous   FIFO has been considered to avoid the complex handshaking mechanism. The design has been implemented within VHDL and implemented on Xilinx Virtex 4.
Volume: 6
Issue: 1
Page: 41-47
Publish at: 2018-05-28

MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN

10.11591/ijres.v6.i2.pp120-126
Ramesh Pawase , N.P. Futane
Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed.  A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization.  The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.
Volume: 6
Issue: 2
Page: 120-126
Publish at: 2018-05-28

FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits

10.11591/ijres.v6.i1.pp53-68
G. Durga Prasad , V Jegathesan
Multilevel converters tender advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation and have been widely accepted for high-power high-voltage applications.  This paper introduces topology in multilevel dc link inverter (MLDCLI), which can significantly reduce the switch count and improve the performance. The preferred topology provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, to the bridge inverter, which in turn gives the required alternating waveform. This topology requires fewer components compared to traditional Multi level Inverters (MLI).Therefore, the overall cost and complexity are significantly reduced particularly for higher output voltage levels. Finally, Matlab/Simulink and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. Simulation and experimental results for fifteen-level inverter are presented for validation.
Volume: 6
Issue: 1
Page: 53-68
Publish at: 2018-05-28

FPGA-based Architecture of Direct Torque Control

10.11591/ijres.v6.i1.pp20-27
Azaza Maher , Echaieb Kamel , Mami Abdelkader
This paper presents an optimized FPGA architecture of a DTC “direct torque control” drive of an induction motor. The proposed architecture is based on variable fixed point world size and the use ipcores in order to achieve higher sampling frequency which leads to reduce the electromagnetic torque and flux ripples. The hardware implementation was experimentally validated, the results shows the effectiveness of the hardware DTC drive implementation by the minimization of the torque and flux ripple
Volume: 6
Issue: 1
Page: 20-27
Publish at: 2018-05-28

Minimizing the loses of solar power generation by designing an intelligent tracking system implemented on FPGA

10.11591/ijres.v6.i3.pp169-178
Alaa Hamza Omran
The increasing of using of an electrical power as a power source in a large number of devices can occur a serious problem in our daily life. One of the useful power sources is a solar cell which used to overcome many problems of power generation. In this paper, the solar cell model is proposed to minimize loses of solar power generation by designing of an intelligent tracking system based on FPGA. PSO algorithms are used to train the neural networks to control the speeds and the directions of rotations of two DC motors with the help of FPGA cart. The proposed system was implemented in MATLAB; and for the hardware part, FPGA was used for the implementation of neural networks.
Volume: 6
Issue: 3
Page: 169-178
Publish at: 2018-05-28

CMOS Active Inductor Based Voltage Controlled Oscillator

10.11591/ijres.v6.i2.pp97-104
Dhara P Patel , Shruti Oza , Rajesh A Thakker
A Tunable Active Inductor (TAI) based Voltage Controlled Oscillator (VCO) for Radio Frequency (RF) applications ranging from 670 MHz - 1.53 GHz is presented. A design of low phase noise and compact VCO is proposed. In order to lower the phase noise of VCO, its RF output power has been improved. The use of low voltage active in-ductor circuit reduces the power dissipation of VCO. The single ended CMOS active inductors with minimum number of transistors are used to consume less die area of VCO circuit. The low power dissipation of the circuit have high efficiency to generate output RF power. A supply independent variable current source tunes the VCO. The post layout design is simulated in Cadence spectreRF using TSMC 180 nm process libraries. The VCO circuit shows the phase noise variation from -124 to  - 126 dBc/Hz and an active area of 0.0049 mm2. The VCO core circuit, excluding output buffers, consumes 10 mW at 1.8 V supply voltage.
Volume: 6
Issue: 2
Page: 97-104
Publish at: 2018-05-28

FPGA implementation of DS-CDMA Transmitter and Receiver

10.11591/ijres.v6.i3.pp179-185
Harinath Mandalapu , B Murali Krishna
Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.
Volume: 6
Issue: 3
Page: 179-185
Publish at: 2018-05-28

NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm

10.11591/ijres.v6.i2.pp105-110
A. Kalimuthu , M. Karthikeyan
A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique
Volume: 6
Issue: 2
Page: 105-110
Publish at: 2018-05-28

ARM Controller and EEG based Drowsiness Tracking and Controlling during Driving

10.11591/ijres.v6.i3.pp127-132
B. Naresh , S. Rambabu , D. Khalandar Basha
This paper discussed about EEG-Based Drowsiness Tracking during Distracted Driving based on Brain computer interfaces (BCI). BCIs are systems that can bypass conventional channels of communication (i.e., muscles and thoughts) to provide direct communication and control between the human brain and physical devices by translating different patterns of brain activity commands through controller device in real time. With these signals from brain in mat lab signals spectrum analyzed and estimates driver concentration and meditation conditions. If there is any nearest vehicles to this vehicle a voice alert given to driver for alert. And driver going to sleep gives voice alert for driver using voice chip. And give the information about traffic signal indication using RFID. The patterns of interaction between these neurons are represented as thoughts and emotional states. According to the human feelings, this pattern will be changing which in turn produce different electrical waves. A muscle contraction will also generate a unique electrical signal. All these electrical waves will be sensed by the brain wave sensor and it will convert the data into packets and transmit through Bluetooth medium. Level analyzer unit (LAU) is used to receive the raw data from brain wave sensor and it is used to extract and process the signal using Mat lab platform. The nearest vehicles information is information is taken through ultrasonic sensors and gives voice alert. And traffic signals condition is detected through RF technology.
Volume: 6
Issue: 3
Page: 127-132
Publish at: 2018-05-28

Software and Hardware for managing Scratch Pad Memory

10.11591/ijres.v6.i2.pp69-81
Chabane Hemdani , Rachida Aoudjit , Mustapha Lalam , Khaled Slimani
This paper proposes a low-cost architecture to improve the management SPM (Scratch Pad Memory) in dynamic and multitasking modes. In this context, our management strategy SPM based on Programmable Automaton implemented in Xilinx Vertex-5 FPGA is entirely different from prior research works. SPM is generally managed by software (by a strong programming logic or by compilation). But our Programmable Automaton facilitates access to SPM in order to move code or data and liberates space in SPM. After this step, software takes over content management of SPM (what part of code or data should be placed in SPM, locates spaces of Heap and Stack). So the performance of the programs is actually improved thanks to minimization of the access latency at the DRAM (Dynamic Random Access Memory or Main Memory).
Volume: 6
Issue: 2
Page: 69-81
Publish at: 2018-05-28

FPGA based Implementation of Symmetrical Reduced Switch Multilevel Inverter

10.11591/ijres.v6.i1.pp28-35
K. Venkataramanan , B. Shanthi , T. S. Sivakumaran
Multilevel inverter has become more popular and attractive for drive applications. Among the various modulation techniques, Carrier based techniques has been commonly used because of their simplicity and flexibility. This paper presents the comparisons of bipolar multicarrier pulse width modulation for the new symmetrical multilevel inverter. The performance parameters of new multilevel inverter were analyzed through various switching strategies. The detailed study has been carried out by MATLAB/SIMULINK. The real time implementation was carried out using FPGA. The results of both simulation and experimentation were compared.
Volume: 6
Issue: 1
Page: 28-35
Publish at: 2018-05-28

Optimization of Resource Utilization of Fast Fourier Transform

10.11591/ijres.v6.i3.pp186-190
Subhash Chandra Yadav , Pradeep Juneja , R. G. Varshney
This paper considers the optimization of resource utilization for three FFT algorithms, as it pertains not to the input samples or output modes, but to the twiddle factors that arise in Cooley-Tukey FFT algorithms. Twiddle factors are a set of complex roots of unity, fixed by the transform order for the particular algorithm. This paper shows the comparison between three known FFT algorithms, DIT-FFT, DIF-FFT and GT algorithm. All these algorithms are implemented on FPGA (Spartan-3 XC3S4000l-4fg900) with XILINX 10.1 ISE.
Volume: 6
Issue: 3
Page: 186-190
Publish at: 2018-05-28

Using FPGA Design and HIL Algorithm Simulation to Control Visual Servoing

10.11591/ijres.v6.i2.pp111-119
Lway Faisal Abdulrazak , Zaid A. Aljawary
This is a novel research paper provides an optimal solution for object tracking using visual servoing control system with programmable gate array technology to realize the visual controller. The controller takes in account the robot dynamics to generate the joint torques directly for performing the tasks related to object tracking using visual servoing. Also, the notion of dynamic perceptibility provides the capability of the designed system to track desired objects employing direct visual servoing technique. This idea is assimilated in the suggested controller and realized in the programmable gate array. Additionally, this paper grants an ideal control framework for direct visual servoing robots that incorporates dynamic perceptibility features. With the aim of evaluating the proposed FPGA based architecture, the control algorithm is applied to Hardware-in-the-loop simulation (HIL) set up of three degrees of freedom rigid robotic manipulator with three links. Furthermore, different investigations are performed to demonstrate the behavior of the proposed system when a trajectory adjacent to a singularity is attained.
Volume: 6
Issue: 2
Page: 111-119
Publish at: 2018-05-28

Android Based Switch Controlling Technique for LED Bulbs Using Bluetooth/Wi-Fi Technology

10.11591/ijres.v6.i1.pp48-52
Munigoti Saikiran , Lalith Nagaram Nagarajan , Malladi Bharath
This paper presents an efficient approach to switch on/off and control the intensity of an LED bulb from a remote place using Android Applications installed in a Smartphone. As LED household bulbs and lights are energy efficient, drop-in replacements for the incandescent lighting found in homes and offices. These lights produce a warm brightness while providing a significant cost savings over traditional lighting. Bluetooth & Wi-Fi modules are used simultaneously as an interface that make connection between Android Application and the LPC2148 controller by which the generated output can be viewed with the help of an LED bulb and control various other devices, based on the availability in particular areas.
Volume: 6
Issue: 1
Page: 48-52
Publish at: 2018-05-28
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